From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 09:07:13 +0000 (+0000)
Subject: move round to function
X-Git-Tag: ls180-24jan2020~1963
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20a9b26e19454870baec6db9fb9e82d0987df560;p=ieee754fpu.git

move round to function
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index af947149..676d8381 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -153,6 +153,13 @@ class FPADD:
         with m.Else():
             m.next = next_state
 
+    def round(self, m, z, of, next_state):
+        m.next = next_state
+        with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
+            m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
+            with m.If(z.m == z.m1s): # all 1s
+                m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
+
     def get_fragment(self, platform=None):
         m = Module()
 
@@ -329,11 +336,7 @@ class FPADD:
             # rounding stage
 
             with m.State("round"):
-                m.next = "corrections"
-                with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
-                    m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
-                    with m.If(z.m == z.m1s): # all 1s
-                        m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
+                self.round(m, z, of, "corrections")
 
             # ******
             # correction stage