From: Chris Demetriou Date: Mon, 11 Feb 2002 02:19:38 +0000 (+0000) Subject: 2002-02-10 Chris Demetriou cgd@sibyte.com X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20ae00985d69195b9f777f19fe0c113672ba2f1c;p=binutils-gdb.git 2002-02-10 Chris Demetriou cgd@sibyte.com * mips.igen (ADDI): Print immediate value. (BREAK): Print code. (DADDIU, DSRAV, DSRLV): Print correct instruction name. (SLL): Print "nop" specially, and don't run the code that does the shift for the "nop" case. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 6a5f08f395f..b9d81c5eccd 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,11 @@ +2002-02-10 Chris Demetriou cgd@sibyte.com + + * mips.igen (ADDI): Print immediate value. + (BREAK): Print code. + (DADDIU, DSRAV, DSRLV): Print correct instruction name. + (SLL): Print "nop" specially, and don't run the code + that does the shift for the "nop" case. + 2001-11-17 Fred Fish * sim-main.h (float_operation): Move enum declaration outside diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 03f783a2be2..3ed8f62fc65 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -245,7 +245,7 @@ 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI -"addi r, r, IMMEDIATE" +"addi r, r, " *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: @@ -668,7 +668,7 @@ 000000,20.CODE,001101:SPECIAL:32::BREAK -"break" +"break " *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: @@ -747,7 +747,7 @@ } 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU -"daddu r, r, " +"daddiu r, r, " *mipsIII: *mipsIV: *vr4100: @@ -1113,7 +1113,7 @@ } 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV -"dsra32 r, r, r" +"dsrav r, r, r" *mipsIII: *mipsIV: *vr4100: @@ -1160,7 +1160,7 @@ 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV -"dsrl32 r, r, r" +"dsrlv r, r, r" *mipsIII: *mipsIV: *vr4100: @@ -2012,13 +2012,17 @@ } 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL +"nop":RD == 0 && RT == 0 && SHIFT == 0 "sll r, r, " *mipsI,mipsII,mipsIII,mipsIV: *vr4100: *vr5000: *r3900: { - do_sll (SD_, RT, RD, SHIFT); + /* Skip shift for NOP, so that there won't be lots of extraneous + trace output. */ + if (RD != 0 || RT != 0 || SHIFT != 0) + do_sll (SD_, RT, RD, SHIFT); }