From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Oct 2020 15:58:14 +0000 (+0100)
Subject: add SRR1 setting for LDST memory exception trap
X-Git-Tag: 24jan2021_ls180~208
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20afbd096e75c1fa88f6ba07a5d7804b76b8a971;p=soc.git

add SRR1 setting for LDST memory exception trap
---

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 56129099..25ce8758 100644
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -119,6 +119,8 @@ botchify(MSRb, MSR)
 
 # use this in the simulator
 class PIb:
+    INVALID      = 33    # 1 for an invalid mem err
+    PERMERR      = 35    # 1 for an permanent mem err
     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
     FP           = 43    # 1 if FP exception
     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index b581922b..60a49d4f 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -911,10 +911,10 @@ class PowerDecode2(PowerDecodeSubset):
         # after a failed LD/ST.
         with m.If(exc.happened):
             with m.If(exc.alignment):
-                self.trap(m, TT.MEMEXC, 0x600)
+                self.trap(m, TT.PRIV, 0x600)
             with m.Elif(exc.instr_fault):
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x480)
+                    self.trap(m, TT.PRIV, 0x480)
                 with m.Else():
                     # TODO
                     #srr1(63 - 33) <= exc.invalid;
@@ -924,9 +924,9 @@ class PowerDecode2(PowerDecodeSubset):
                     self.trap(m, TT.MEMEXC, 0x400, exc)
             with m.Else():
                 with m.If(exc.segment_fault):
-                    self.trap(m, TT.MEMEXC, 0x380)
+                    self.trap(m, TT.PRIV, 0x380)
                 with m.Else():
-                    self.trap(m, TT.MEMEXC, 0x300)
+                    self.trap(m, TT.PRIV, 0x300)
 
         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
         with m.Elif(dec_irq_ok):
diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 3c609cf1..95dabe7f 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -15,6 +15,7 @@ from nmutil.extend import exts
 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
 from soc.fu.branch.main_stage import br_ext
 from soc.decoder.power_enums import MicrOp
+from soc.experiment.mem_types import LDSTException
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
@@ -195,6 +196,14 @@ class TrapMainStage(PipeModBase):
                         comb += srr1_o.data[PI.FP].eq(1)
                     with m.If(traptype & TT.ADDR):
                         comb += srr1_o.data[PI.ADR].eq(1)
+                    with m.If(traptype & TT.MEMEXC):
+                        # decode exception bits, store in SRR1
+                        exc = LDSTException("trapexc")
+                        comb += exc.eq(op.ldst_exc)
+                        comb += srr1_o.data[PI.INVALID].eq(exc.invalid)
+                        comb += srr1_o.data[PI.PERMERR].eq(exc.perm_error)
+                        comb += srr1_o.data[PI.ILLEG].eq(exc.badtree)
+                        comb += srr1_o.data[PI.PRIV].eq(exc.rc_error)
                     with m.If(traptype & TT.EINT):
                         # do nothing unusual? see 3.0B Book III 6.5.7 p1073
                         pass