From: José Fonseca <jfonseca@vmware.com>
Date: Tue, 15 Jul 2014 13:47:20 +0000 (+0100)
Subject: util/tgsi: Fix ureg_EMIT/ENDPRIM prototype.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20b431fd9eafa1336edbb9b1ab80327e2fce3532;p=mesa.git

util/tgsi: Fix ureg_EMIT/ENDPRIM prototype.

0cbefc1bea703378381afff946e30c27a21f191d added a source argument to
EMIT/ENDPRIM, but it did not update tgsi_ureg accordingly, causing all
users of ureg_EMIT/ENDPRIM to fail at runtime with an assertion failure.

Trivial.
---

diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
index cc5c03bd457..7888be86702 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
@@ -146,8 +146,8 @@ OP13(SAD)
 OP12_TEX(TXF)
 OP12_TEX(TXQ)
 OP00(CONT)
-OP00(EMIT)
-OP00(ENDPRIM)
+OP01(EMIT)
+OP01(ENDPRIM)
 OP00_LBL(BGNLOOP)
 OP00(BGNSUB)
 OP00_LBL(ENDLOOP)