From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 22:53:40 +0000 (-0800)
Subject: Remove check for cell->name[0] == '$'
X-Git-Tag: yosys-0.9~313^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20ca795b87b810063cdcee6e92e3922281f6b092;p=yosys.git

Remove check for cell->name[0] == '$'
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 66a9e70d3..7b3a60e61 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
 	std::string init;
-	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
 		init = ss.str();