From: Luke Kenneth Casson Leighton Date: Sat, 29 Apr 2023 17:31:50 +0000 (+0100) Subject: clarify fdmadds wording in twin_butterfly.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20eabe694d1cc915fa354112aef1680247c4a407;p=libreriscv.git clarify fdmadds wording in twin_butterfly.mdwn --- diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn index a125cea00..aa8048353 100644 --- a/openpower/sv/twin_butterfly.mdwn +++ b/openpower/sv/twin_butterfly.mdwn @@ -171,13 +171,14 @@ operand in register FRB and the result stored in FRS. Using the exact same operand input register values from FRT and FRB that were used to create FRS, the Floating-Point operand in register FRB is subtracted from the floating-point operand in register FRT and -the result then multiplied by FRA to create an intermediate result that -is stored in FRT. +the result then rounded before being multiplied by FRA to create an +intermediate result that is stored in FRT. The add into FRS is treated exactly as `fadds`. The creation of the -result FRT is **not** the same as that of `fmsubs`. -The creation of FRS and FRT are treated as parallel independent operations -which occur at the same time. +result FRT is **not** the same as that of `fmsubs`, but is instead as if +`fsubs` were performed first followed by `fmuls`. The creation of FRS +and FRT are treated as parallel independent operations which occur at +the same time. Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED` @@ -290,13 +291,14 @@ operand in register FRB and the result stored in FRS. Using the exact same operand input register values from FRT and FRB that were used to create FRS, the Floating-Point operand in register FRB is subtracted from the floating-point operand in register FRT and -the result then multiplied by FRA to create an intermediate result that -is stored in FRT. +the result then rounded before being multiplied by FRA to create an +intermediate result that is stored in FRT. The add into FRS is treated exactly as `fadd`. The creation of the -result FRT is **not** the same as that of `fmsub`. -The creation of FRS and FRT are treated as parallel independent operations -which occur at the same time. +result FRT is **not** the same as that of `fmsub`, but is instead as if +`fsub` were performed first followed by `fmuls. The creation of FRS +and FRT are treated as parallel independent operations which occur at +the same time. Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED`