From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Date: Tue, 14 Apr 2020 20:59:41 +0000 (-0400)
Subject: pan/bit: Add fexp2_fast interp
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20f255b18e48f61a5a0b22041c7149225f3bed64;p=mesa.git

pan/bit: Add fexp2_fast interp

Kind of a hack and not at all how the h/w does it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
---

diff --git a/src/panfrost/bifrost/test/bi_interpret.c b/src/panfrost/bifrost/test/bi_interpret.c
index 9e88795b324..1d7b51bba17 100644
--- a/src/panfrost/bifrost/test/bi_interpret.c
+++ b/src/panfrost/bifrost/test/bi_interpret.c
@@ -489,7 +489,14 @@ bit_step(struct bit_state *s, bi_instruction *ins, bool FMA)
 
         case BI_SPECIAL: {
                 assert(nir_alu_type_get_base_type(ins->dest_type) == nir_type_float);
-                assert(nir_alu_type_get_base_type(ins->dest_type) != nir_type_float64);
+                assert(ins->dest_type != nir_type_float64);
+
+                if (ins->op.special == BI_SPECIAL_EXP2_LOW) {
+                        assert(ins->dest_type == nir_type_float32);
+                        dest.f32 = exp2f(srcs[1].f32);
+                        break;
+                }
+
                 float Q = (ins->dest_type == nir_type_float16) ?
                         bf(srcs[0].u16[ins->swizzle[0][0]]) :
                         srcs[0].f32;