From: WANG Xuerui <git@xen0n.name>
Date: Wed, 27 Jul 2022 11:07:57 +0000 (+0800)
Subject: opcodes: LoongArch: add "ret" instruction to reduce typing
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20f2e2686c79a5ac951f0cc283f385c16bda5d50;p=binutils-gdb.git

opcodes: LoongArch: add "ret" instruction to reduce typing

This syntactic sugar is present in both classical and emerging
architectures, like Alpha, SPARC and RISC-V, and assembler macros
doing the same thing can already be found in the wild e.g. [1], proving
the feature's popularity. It's better to provide support directly in the
assembler so downstream users wouldn't have to re-invent this over and
over again.

[1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
---

diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index b10390f640f..218c13f9398 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -28,3 +28,4 @@ Disassembly of section .text:
 [ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0x0
 [ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0x0
 [ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0x0
+[ 	]+54:[ 	]+4c000020[ 	]+[ 	]+jirl[ 	]+\$zero, \$ra, 0
diff --git a/gas/testsuite/gas/loongarch/jmp_op.s b/gas/testsuite/gas/loongarch/jmp_op.s
index 1deb165aeba..56f986784e2 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.s
+++ b/gas/testsuite/gas/loongarch/jmp_op.s
@@ -20,3 +20,4 @@ bltu  $r4,$r5,.L1
 bgtu  $r4,$r5,.L1
 bgeu  $r4,$r5,.L1
 bleu  $r4,$r5,.L1
+ret
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index b10390f640f..218c13f9398 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -28,3 +28,4 @@ Disassembly of section .text:
 [ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0x0
 [ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0x0
 [ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0x0
+[ 	]+54:[ 	]+4c000020[ 	]+[ 	]+jirl[ 	]+\$zero, \$ra, 0
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loongarch-elf/jmp_op.s
index 1deb165aeba..56f986784e2 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.s
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.s
@@ -20,3 +20,4 @@ bltu  $r4,$r5,.L1
 bgtu  $r4,$r5,.L1
 bgeu  $r4,$r5,.L1
 bleu  $r4,$r5,.L1
+ret
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 35bae8c3ed4..1b510048c29 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -841,6 +841,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
   { 0x0,	0x0,		"bgtu",		"r,r,la",			"bltu %2,%1,%%b16(%3)",		0, 0, 0 },
   { 0x0,	0x0,		"bleu",		"r,r,la",			"bgeu %2,%1,%%b16(%3)",		0, 0, 0 },
   { 0x0,	0x0,		"jr",		"r",				"jirl $r0,%1,0",		0, 0, 0 },
+  { 0x0,	0x0,		"ret",		"",				"jirl $r0,$r1,0",		0, 0, 0 },
   { 0 } /* Terminate the list.  */
 };