From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 18:24:19 +0000 (-0700)
Subject: Merge branch 'master' into mwk/xilinx_bufgmap
X-Git-Tag: working-ls180~1097^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20f4d191b53544049357401408d5d0c2b2ddcca4;p=yosys.git

Merge branch 'master' into mwk/xilinx_bufgmap
---

20f4d191b53544049357401408d5d0c2b2ddcca4
diff --cc techlibs/xilinx/cells_sim.v
index f1e019d1e,3ad96d7fb..aeef7f885
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -340,10 -324,9 +340,10 @@@ module RAM64X1D 
    output DPO, SPO,
    (* abc_scc_break *)
    input  D,
 +  (* clkbuf_sink *)
    input  WCLK,
    (* abc_scc_break *)
-   input WE,
+   input  WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
  );