From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 7 Dec 2021 03:33:25 +0000 (-0800)
Subject: make bitmanip operations conditional on pspec.draft_bitmanip
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=20ffa8ec223be44fc37df5184ca09d648e85a844;p=soc.git

make bitmanip operations conditional on pspec.draft_bitmanip
---

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index 7437d811..40220a1c 100644
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -81,3 +81,8 @@ class CommonPipeSpec:
         self.opkls = lambda _: self.opsubsetkls()
         self.op_wid = get_rec_width(self.opkls(None))  # hmm..
         self.stage = None
+        self.draft_bitmanip = False
+
+
+def get_pspec_draft_bitmanip(pspec):
+    return getattr(pspec, "draft_bitmanip", False)
diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 3f059b94..1d2f1735 100644
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -8,6 +8,7 @@
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
+from soc.fu.pipe_data import get_pspec_draft_bitmanip
 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
                                         ShiftRotInputData)
 from nmutil.lut import BitwiseLut
@@ -21,6 +22,7 @@ from openpower.decoder.power_fieldsn import SignalBitRange
 class ShiftRotMainStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "main")
+        self.draft_bitmanip = get_pspec_draft_bitmanip(pspec)
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
@@ -36,11 +38,13 @@ class ShiftRotMainStage(PipeModBase):
         op = self.i.ctx.op
         o = self.o.o
 
-        bitwise_lut = BitwiseLut(input_count=3, width=64)
-        m.submodules.bitwise_lut = bitwise_lut
-        comb += bitwise_lut.inputs[0].eq(self.i.rb)
-        comb += bitwise_lut.inputs[1].eq(self.i.ra)
-        comb += bitwise_lut.inputs[2].eq(self.i.rc)
+        bitwise_lut = None
+        if self.draft_bitmanip:
+            bitwise_lut = BitwiseLut(input_count=3, width=64)
+            m.submodules.bitwise_lut = bitwise_lut
+            comb += bitwise_lut.inputs[0].eq(self.i.rb)
+            comb += bitwise_lut.inputs[1].eq(self.i.ra)
+            comb += bitwise_lut.inputs[2].eq(self.i.rc)
 
         # NOTE: the sh field immediate is read in by PowerDecode2
         # (actually DecodeRB), whereupon by way of rb "immediate" mode
@@ -95,12 +99,13 @@ class ShiftRotMainStage(PipeModBase):
                 comb += mode.eq(0b0100)  # clear R
             with m.Case(MicrOp.OP_EXTSWSLI):
                 comb += mode.eq(0b1000)  # L-ext
-            with m.Case(MicrOp.OP_TERNLOG):
-                # TODO: this only works for ternaryi, change to get lut value
-                # from register when we implement other variants
-                comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
-                comb += o.data.eq(bitwise_lut.output)
-                comb += self.o.xer_ca.data.eq(0)
+            if self.draft_bitmanip:
+                with m.Case(MicrOp.OP_TERNLOG):
+                    # TODO: this only works for ternlogi, change to get lut
+                    # value from register when we implement other variants
+                    comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
+                    comb += o.data.eq(bitwise_lut.output)
+                    comb += self.o.xer_ca.data.eq(0)
             with m.Default():
                 comb += o.ok.eq(0)  # otherwise disable
 
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index c0e16ba6..00bb3262 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -71,6 +71,7 @@ class ShiftRotIlangCase(TestAccumulatorBase):
 
     def case_ilang(self):
         pspec = ShiftRotPipeSpec(id_wid=2)
+        pspec.draft_bitmanip = True
         alu = ShiftRotBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("shift_rot_pipeline.il", "w") as f:
@@ -137,6 +138,7 @@ class TestRunner(unittest.TestCase):
         pdecode = pdecode2.dec
 
         pspec = ShiftRotPipeSpec(id_wid=2)
+        pspec.draft_bitmanip = True
         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)