From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 4 Feb 2022 13:37:08 +0000 (+0000)
Subject: get arty a7-100t functional
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21100754d3be6a764880c23a7ed0af6f5da8f5de;p=libresoc-litex.git

get arty a7-100t functional
---

diff --git a/Makefile b/Makefile
index 1bfeeb3..18916ed 100644
--- a/Makefile
+++ b/Makefile
@@ -42,3 +42,7 @@ versaecp5:
 
 versaecp5load:
 	./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+artya7100t:
+	python3 ./versa_ecp5.py --sys-clk-freq=100e6 --build  --fpga=artya7100t \
+                    --toolchain=symbiflow
diff --git a/README.txt b/README.txt
index 3d008eb..b7eb141 100644
--- a/README.txt
+++ b/README.txt
@@ -13,3 +13,10 @@ same thing: first build libresoc.v and copy it to the libresoc/ directory
 
 ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
 ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+# arty a7 build
+
+export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
+./versa_ecp5.py --sys-clk-freq=100e6 --build  --fpga=artya7100t \
+                    --toolchain=symbiflow
+
diff --git a/sim.py b/sim.py
index 44fcf1b..f4ec8dc 100755
--- a/sim.py
+++ b/sim.py
@@ -59,10 +59,10 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = "/tmp/test.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
-        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-        #            "tests/xics/xics.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/decrementer/decrementer.bin"
+                    "tests/xics/xics.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
diff --git a/versa_ecp5.py b/versa_ecp5.py
index 73f3dcd..4b6b128 100755
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -6,6 +6,9 @@ import sys
 
 import litex_boards.targets.versa_ecp5 as versa_ecp5
 import litex_boards.targets.ulx3s as ulx3s
+#import litex_boards.targets.arty as arty
+import digilent_arty as arty
+
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex.soc.integration.soc_sdram import (soc_sdram_args,
@@ -110,6 +113,27 @@ class ULX3S85FTestSoC(ulx3s.BaseSoC):
         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 
+
+class ArtyTestSoC(arty.BaseSoC):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+        kwargs["integrated_rom_size"] = 0x10000
+        #kwargs["integrated_main_ram_size"] = 0x1000
+        kwargs["csr_data_width"] = 32
+        kwargs['csr_address_width'] = 15 # limit to 0x8000
+        kwargs["l2_size"] = 0
+        #bus_data_width = 16,
+
+        arty.BaseSoC.__init__(self,
+            sys_clk_freq = sys_clk_freq,
+            cpu_type     = "external",
+            cpu_cls      = LibreSoC,
+            cpu_variant  = "standardjtag",
+            #cpu_cls      = Microwatt,
+            variant      = "a7-100",
+            toolchain    = "symbiflow",
+            **kwargs)
+
+
 # Build
 # ----------------------------------------------------------------------------
 
@@ -126,18 +150,23 @@ def main():
     parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
 
     builder_args(parser)
-    trellis_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
     if args.fpga == "versa_ecp5":
+        trellis_args(parser)
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))
 
     elif args.fpga == "ulx3s85f":
+        trellis_args(parser)
         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                               **soc_sdram_argdict(args))
 
+    elif args.fpga == "artya7100t":
+        soc = ArtyTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+                              **soc_sdram_argdict(args))
+
     else:
         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
                                **soc_sdram_argdict(args))