From: Jacob Lifshay Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700) Subject: split out instructions from openpower/isa/fixedsync.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21187768101581f768c4b2c65dc8348d08372605;p=openpower-isa.git split out instructions from openpower/isa/fixedsync.mdwn --- diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn index 5667c07f..74c518ca 100644 --- a/openpower/isa/fixedsync.mdwn +++ b/openpower/isa/fixedsync.mdwn @@ -2,138 +2,20 @@ -# Instruction Synchronise +[[!inline pagenames="openpower/isa/fixedsync/isync" raw="yes"]] -XL-Form +[[!inline pagenames="openpower/isa/fixedsync/lbarx" raw="yes"]] -* isync +[[!inline pagenames="openpower/isa/fixedsync/lharx" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedsync/lwarx" raw="yes"]] - # TODO - undefined(0) +[[!inline pagenames="openpower/isa/fixedsync/ldarx" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedsync/stbcx." raw="yes"]] - None +[[!inline pagenames="openpower/isa/fixedsync/sthcx." raw="yes"]] -# Load Byte And Reserve Indexed - -X-Form - -* lbarx RT,RA,RB,EH - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - None - -# Load Halfword And Reserve Indexed - -X-Form - -* lharx RT,RA,RB,EH - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - None - -# Load Word And Reserve Indexed - -X-Form - -* lwarx RT,RA,RB,EH - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - None - -# Load Doubleword And Reserve Indexed - -X-Form - -* ldarx RT,RA,RB,EH - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - None - -# Store Byte Conditional Indexed - -X-Form - -* stbcx. RS,RA,RB - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - CR0 - -# Store Halfword Conditional Indexed - -X-Form - -* sthcx. RS,RA,RB - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - CR0 - -# Store word Conditional Indexed - -X-Form - -* stwcx. RS,RA,RB - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - CR0 - -# Store Doubleword Conditional Indexed - -X-Form - -* stdcx. RS,RA,RB - -Pseudo-code: - - # TODO - undefined(0) - -Special Registers Altered: - - CR0 +[[!inline pagenames="openpower/isa/fixedsync/stwcx." raw="yes"]] +[[!inline pagenames="openpower/isa/fixedsync/stdcx." raw="yes"]] diff --git a/openpower/isa/fixedsync/isync.mdwn b/openpower/isa/fixedsync/isync.mdwn new file mode 100644 index 00000000..9476652b --- /dev/null +++ b/openpower/isa/fixedsync/isync.mdwn @@ -0,0 +1,13 @@ +# Instruction Synchronise + +XL-Form + +* isync + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/isync_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedsync/isync_code.mdwn b/openpower/isa/fixedsync/isync_code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/isync_code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/lbarx.mdwn b/openpower/isa/fixedsync/lbarx.mdwn new file mode 100644 index 00000000..0ace9373 --- /dev/null +++ b/openpower/isa/fixedsync/lbarx.mdwn @@ -0,0 +1,13 @@ +# Load Byte And Reserve Indexed + +X-Form + +* lbarx RT,RA,RB,EH + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/lbarx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedsync/lbarx_code.mdwn b/openpower/isa/fixedsync/lbarx_code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/lbarx_code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/ldarx.mdwn b/openpower/isa/fixedsync/ldarx.mdwn new file mode 100644 index 00000000..e423183c --- /dev/null +++ b/openpower/isa/fixedsync/ldarx.mdwn @@ -0,0 +1,13 @@ +# Load Doubleword And Reserve Indexed + +X-Form + +* ldarx RT,RA,RB,EH + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/ldarx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedsync/ldarx_code.mdwn b/openpower/isa/fixedsync/ldarx_code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/ldarx_code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/lharx.mdwn b/openpower/isa/fixedsync/lharx.mdwn new file mode 100644 index 00000000..5d4dfdca --- /dev/null +++ b/openpower/isa/fixedsync/lharx.mdwn @@ -0,0 +1,13 @@ +# Load Halfword And Reserve Indexed + +X-Form + +* lharx RT,RA,RB,EH + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/lharx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedsync/lharx_code.mdwn b/openpower/isa/fixedsync/lharx_code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/lharx_code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/lwarx.mdwn b/openpower/isa/fixedsync/lwarx.mdwn new file mode 100644 index 00000000..766a8cc7 --- /dev/null +++ b/openpower/isa/fixedsync/lwarx.mdwn @@ -0,0 +1,13 @@ +# Load Word And Reserve Indexed + +X-Form + +* lwarx RT,RA,RB,EH + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/lwarx_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedsync/lwarx_code.mdwn b/openpower/isa/fixedsync/lwarx_code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/lwarx_code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/stbcx..mdwn b/openpower/isa/fixedsync/stbcx..mdwn new file mode 100644 index 00000000..8ac78202 --- /dev/null +++ b/openpower/isa/fixedsync/stbcx..mdwn @@ -0,0 +1,13 @@ +# Store Byte Conditional Indexed + +X-Form + +* stbcx. RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/stbcx._code" raw="yes"]] + +Special Registers Altered: + + CR0 diff --git a/openpower/isa/fixedsync/stbcx._code.mdwn b/openpower/isa/fixedsync/stbcx._code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/stbcx._code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/stdcx..mdwn b/openpower/isa/fixedsync/stdcx..mdwn new file mode 100644 index 00000000..f66f59ea --- /dev/null +++ b/openpower/isa/fixedsync/stdcx..mdwn @@ -0,0 +1,14 @@ +# Store Doubleword Conditional Indexed + +X-Form + +* stdcx. RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/stdcx._code" raw="yes"]] + +Special Registers Altered: + + CR0 + diff --git a/openpower/isa/fixedsync/stdcx._code.mdwn b/openpower/isa/fixedsync/stdcx._code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/stdcx._code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/sthcx..mdwn b/openpower/isa/fixedsync/sthcx..mdwn new file mode 100644 index 00000000..d687349b --- /dev/null +++ b/openpower/isa/fixedsync/sthcx..mdwn @@ -0,0 +1,13 @@ +# Store Halfword Conditional Indexed + +X-Form + +* sthcx. RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/sthcx._code" raw="yes"]] + +Special Registers Altered: + + CR0 diff --git a/openpower/isa/fixedsync/sthcx._code.mdwn b/openpower/isa/fixedsync/sthcx._code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/sthcx._code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0) diff --git a/openpower/isa/fixedsync/stwcx..mdwn b/openpower/isa/fixedsync/stwcx..mdwn new file mode 100644 index 00000000..469ba5ee --- /dev/null +++ b/openpower/isa/fixedsync/stwcx..mdwn @@ -0,0 +1,13 @@ +# Store word Conditional Indexed + +X-Form + +* stwcx. RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedsync/stwcx._code" raw="yes"]] + +Special Registers Altered: + + CR0 diff --git a/openpower/isa/fixedsync/stwcx._code.mdwn b/openpower/isa/fixedsync/stwcx._code.mdwn new file mode 100644 index 00000000..a1a72687 --- /dev/null +++ b/openpower/isa/fixedsync/stwcx._code.mdwn @@ -0,0 +1,2 @@ + # TODO + undefined(0)