From: Michael Meissner <meissner@linux.ibm.com>
Date: Sat, 27 Jun 2020 05:40:48 +0000 (-0500)
Subject: Add PowerPC tests for power10.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=212475e5757fe3335cba30c9c3eec1707ac0c271;p=gcc.git

Add PowerPC tests for power10.

2020-06-27  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-add.c: New test.
	* gcc.target/powerpc/prefix-si-constant.c: New test.
	* gcc.target/powerpc/prefix-di-constant.c: New test.
	* gcc.target/powerpc/prefix-ds-dq.c: New test.
	* gcc.target/powerpc/prefix-no-update.c: New test.
	* gcc.target/powerpc/prefix-large-dd.c: New test.
	* gcc.target/powerpc/prefix-large-df.c: New test.
	* gcc.target/powerpc/prefix-large-di.c: New test.
	* gcc.target/powerpc/prefix-large-hi.c: New test.
	* gcc.target/powerpc/prefix-large-kf.c: New test.
	* gcc.target/powerpc/prefix-large-qi.c: New test.
	* gcc.target/powerpc/prefix-large-sd.c: New test.
	* gcc.target/powerpc/prefix-large-sf.c: New test.
	* gcc.target/powerpc/prefix-large-si.c: New test.
	* gcc.target/powerpc/prefix-large-udi.c: New test.
	* gcc.target/powerpc/prefix-large-uhi.c: New test.
	* gcc.target/powerpc/prefix-large-uqi.c: New test.
	* gcc.target/powerpc/prefix-large-usi.c: New test.
	* gcc.target/powerpc/prefix-large-v2df.c: New test.
	* gcc.target/powerpc/prefix-large.h: Include file for new tests.
	* gcc.target/powerpc/prefix-pcrel-dd.c: New test.
	* gcc.target/powerpc/prefix-pcrel-df.c: New test.
	* gcc.target/powerpc/prefix-pcrel-di.c: New test.
	* gcc.target/powerpc/prefix-pcrel-hi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-kf.c: New test.
	* gcc.target/powerpc/prefix-pcrel-qi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-sd.c: New test.
	* gcc.target/powerpc/prefix-pcrel-sf.c: New test.
	* gcc.target/powerpc/prefix-pcrel-si.c: New test.
	* gcc.target/powerpc/prefix-pcrel-udi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-uhi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-uqi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-usi.c: New test.
	* gcc.target/powerpc/prefix-pcrel-v2df.c: New test.
	* gcc.target/powerpc/prefix-pcrel.h: Include file for new tests.
	* gcc.target/powerpc/prefix-stack-protect.c: New test.
---

diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-add.c b/gcc/testsuite/gcc.target/powerpc/prefix-add.c
new file mode 100644
index 00000000000..0027406e457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-add.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Test that PADDI is generated to add a large constant.  */
+unsigned long
+add (unsigned long a)
+{
+  return a + 0x12345U;
+}
+
+/* { dg-final { scan-assembler     {\mpaddi\M} } } */
+/* { dg-final { scan-assembler-not {\maddi\M}  } } */
+/* { dg-final { scan-assembler-not {\maddis\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c b/gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c
new file mode 100644
index 00000000000..aca7897cd92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant.  */
+unsigned long long
+large (void)
+{
+  return 0x12345678ULL;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c b/gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c
new file mode 100644
index 00000000000..554cd0c1bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c
@@ -0,0 +1,161 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether we generate a prefixed load/store operation for addresses that
+   don't meet DS/DQ offset constraints.  64-bit is needed for testing the use
+   of the PLWA instruciton.  */
+
+struct packed_struct
+{
+  long long pad;			/* offset  0 bytes.  */
+  unsigned char pad_uc;			/* offset  8 bytes.  */
+  unsigned char uc;			/* offset  9 bytes.  */
+
+  unsigned char pad_sc[sizeof (long long) - sizeof (unsigned char)];
+  unsigned char sc;			/* offset  17 bytes.  */
+
+  unsigned char pad_us[sizeof (long long) - sizeof (signed char)];
+  unsigned short us;			/* offset  25 bytes.  */
+
+  unsigned char pad_ss[sizeof (long long) - sizeof (unsigned short)];
+  short ss;				/* offset 33 bytes.  */
+
+  unsigned char pad_ui[sizeof (long long) - sizeof (short)];
+  unsigned int ui;			/* offset 41 bytes.  */
+
+  unsigned char pad_si[sizeof (long long) - sizeof (unsigned int)];
+  unsigned int si;			/* offset 49 bytes.  */
+
+  unsigned char pad_f[sizeof (long long) - sizeof (int)];
+  float f;				/* offset 57 bytes.  */
+
+  unsigned char pad_d[sizeof (long long) - sizeof (float)];
+  double d;				/* offset 65 bytes.  */
+  __float128 f128;			/* offset 73 bytes.  */
+} __attribute__((packed));
+
+unsigned char
+load_uc (struct packed_struct *p)
+{
+  return p->uc;				/* LBZ 3,9(3).  */
+}
+
+signed char
+load_sc (struct packed_struct *p)
+{
+  return p->sc;				/* LBZ 3,17(3) + EXTSB 3,3.  */
+}
+
+unsigned short
+load_us (struct packed_struct *p)
+{
+  return p->us;				/* LHZ 3,25(3).  */
+}
+
+short
+load_ss (struct packed_struct *p)
+{
+  return p->ss;				/* LHA 3,33(3).  */
+}
+
+unsigned int
+load_ui (struct packed_struct *p)
+{
+  return p->ui;				/* LWZ 3,41(3).  */
+}
+
+int
+load_si (struct packed_struct *p)
+{
+  return p->si;				/* PLWA 3,49(3).  */
+}
+
+float
+load_float (struct packed_struct *p)
+{
+  return p->f;				/* LFS 1,57(3).  */
+}
+
+double
+load_double (struct packed_struct *p)
+{
+  return p->d;				/* LFD 1,65(3).  */
+}
+
+__float128
+load_float128 (struct packed_struct *p)
+{
+  return p->f128;			/* PLXV 34,73(3).  */
+}
+
+void
+store_uc (struct packed_struct *p, unsigned char uc)
+{
+  p->uc = uc;				/* STB 4,9(3).  */
+}
+
+void
+store_sc (struct packed_struct *p, signed char sc)
+{
+  p->sc = sc;				/* STB 4,17(3).  */
+}
+
+void
+store_us (struct packed_struct *p, unsigned short us)
+{
+  p->us = us;				/* STH 4,25(3).  */
+}
+
+void
+store_ss (struct packed_struct *p, signed short ss)
+{
+  p->ss = ss;				/* STH 4,33(3).  */
+}
+
+void
+store_ui (struct packed_struct *p, unsigned int ui)
+{
+  p->ui = ui;				/* STW 4,41(3).  */
+}
+
+void
+store_si (struct packed_struct *p, signed int si)
+{
+  p->si = si;				/* STW 4,49(3).  */
+}
+
+void
+store_float (struct packed_struct *p, float f)
+{
+  p->f = f;				/* STFS 1,57(3).  */
+}
+
+void
+store_double (struct packed_struct *p, double d)
+{
+  p->d = d;				/* STFD 1,65(3).  */
+}
+
+void
+store_float128 (struct packed_struct *p, __float128 f128)
+{
+  p->f128 = f128;			/* PSTXV 34,1(3).  */
+}
+
+/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlbz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mlfd\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlfs\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlha\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mplwa\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstb\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstfd\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mstfs\M}  1 } } */
+/* { dg-final { scan-assembler-times {\msth\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}   2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
new file mode 100644
index 00000000000..d3a35977de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the _Decimal64 type.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
new file mode 100644
index 00000000000..49a049b777a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the double type.  */
+
+#define TYPE double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
new file mode 100644
index 00000000000..399f6967ed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the long long type.  */
+
+#define TYPE long long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
new file mode 100644
index 00000000000..18380cac49b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the short type.  */
+
+#define TYPE short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
new file mode 100644
index 00000000000..a6038bd86ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the _Float128 type.  */
+
+#define TYPE _Float128
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
new file mode 100644
index 00000000000..24cdac16e99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the signed char type.  */
+
+#define TYPE signed char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
new file mode 100644
index 00000000000..beb2d9f62b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the _Decimal32 type.  Note, the _Decimal32 type will not generate any
+   prefixed load or stores, because there is no prefixed load/store instruction
+   to load up a vector register as a zero extended 32-bit integer.  So we count
+   the number of load addresses that are generated.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpli\M}    3 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M} 2 } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
new file mode 100644
index 00000000000..9fde1f0a7a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the float type.  */
+
+#define TYPE float
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
new file mode 100644
index 00000000000..876a013a2ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the _Decimal64 type.  */
+
+#define TYPE int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
new file mode 100644
index 00000000000..e6365d37d0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the unsigned long long type.  */
+
+#define TYPE unsigned long long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
new file mode 100644
index 00000000000..3523767a6f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the unsigned short type.  */
+
+#define TYPE unsigned short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
new file mode 100644
index 00000000000..f251c4a12c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the unsigned char type.  */
+
+#define TYPE unsigned char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
new file mode 100644
index 00000000000..d60036da026
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the unsigned int type.  */
+
+#define TYPE unsigned int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
new file mode 100644
index 00000000000..f6d042f0984
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether prefixed instructions with large numeric offsets are generated
+   for the vector double type.  */
+
+#define TYPE vector double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large.h b/gcc/testsuite/gcc.target/powerpc/prefix-large.h
new file mode 100644
index 00000000000..07b38ae0875
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-large.h
@@ -0,0 +1,40 @@
+/* Common tests for prefixed instructions testing whether we can generate a
+   34-bit offset using 1 instruction.  */
+
+#ifndef TYPE
+#define TYPE unsigned int
+#endif
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#ifndef CONSTANT
+#define CONSTANT	0x12480UL
+#endif
+
+#if DO_ADD
+void
+add (TYPE *p, TYPE a)
+{
+  p[CONSTANT] += a;
+}
+#endif
+
+#if DO_VALUE
+TYPE
+value (TYPE *p)
+{
+  return p[CONSTANT];
+}
+#endif
+
+#if DO_SET
+void
+set (TYPE *p, TYPE a)
+{
+  p[CONSTANT] = a;
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c b/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
new file mode 100644
index 00000000000..837fcd77c0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-no-update.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+   update instructions (i.e. instead of generating LWZU we have to generate
+   PLWZ plus a PADDI).  */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+  unsigned int field;
+  char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
+/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddi\M}     } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c
new file mode 100644
index 00000000000..165aa2f9aa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   _Decimal64 type.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c
new file mode 100644
index 00000000000..b7fd84e7de2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   double type.  */
+
+#define TYPE double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c
new file mode 100644
index 00000000000..90081e452a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   long long type.  */
+
+#define TYPE long long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c
new file mode 100644
index 00000000000..71357b7d149
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   short type.  */
+
+#define TYPE short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c
new file mode 100644
index 00000000000..94bcbdc67d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   _Float128 type.  */
+
+#define TYPE _Float128
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c
new file mode 100644
index 00000000000..472360c08f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   signed char type.  */
+
+#define TYPE signed char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c
new file mode 100644
index 00000000000..94c076d3ed6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   _Decimal32 type.  Note, the _Decimal32 type will not generate any prefixed
+   load or stores, because there is no prefixed load/store instruction to load
+   up a vector register as a zero extended 32-bit integer.  So we count the
+   number of load addresses that are generated.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mpla\M}  3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c
new file mode 100644
index 00000000000..0e907e07d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   float type.  */
+
+#define TYPE float
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c
new file mode 100644
index 00000000000..fb90fcd878f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   int type.  */
+
+#define TYPE int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c
new file mode 100644
index 00000000000..940040fc5aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   unsigned long long type.  */
+
+#define TYPE unsigned long long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c
new file mode 100644
index 00000000000..5c8d082e831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   unsigned short type.  */
+
+#define TYPE unsigned short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c
new file mode 100644
index 00000000000..68999192d54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   unsigned char type.  */
+
+#define TYPE unsigned char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c
new file mode 100644
index 00000000000..5948f8254c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   unsigned int type.  */
+
+#define TYPE unsigned int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c
new file mode 100644
index 00000000000..d626b8a128e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Tests whether pc-relative prefixed instructions are generated for the
+   vector double type.  */
+
+#define TYPE vector double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h
new file mode 100644
index 00000000000..26175dc7d1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h
@@ -0,0 +1,41 @@
+/* Common tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for each type.  */
+
+#ifndef TYPE
+#define TYPE unsigned int
+#endif
+
+static TYPE a;
+
+/* Make sure a is not optimized away.  */
+TYPE *p = &a;
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#if DO_ADD
+void
+add (TYPE b)
+{
+  a += b;
+}
+#endif
+
+#if DO_VALUE
+TYPE
+value (void)
+{
+  return a;
+}
+#endif
+
+#if DO_SET
+void
+set (TYPE b)
+{
+  a = b;
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c b/gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c
new file mode 100644
index 00000000000..6403aa8024c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant for SImode.  */
+void
+large_si (unsigned int *p)
+{
+  *p = 0x12345U;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c b/gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c
new file mode 100644
index 00000000000..ca3b3dfd89f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector-strong" } */
+
+/* Test that we can handle large stack frames with -fstack-protector-strong and
+   prefixed addressing.  This was originally discovered when trying to build
+   glibc with -mcpu=power10, and vfwprintf.c failed because it used
+   -fstack-protector-strong.  It needs 64-bit due to the size of the stack.  */
+
+extern long foo (char *);
+
+long
+bar (void)
+{
+  char buffer[0x20000];
+  return foo (buffer) + 1;
+}
+
+/* { dg-final { scan-assembler {\mpld\M}  } } */
+/* { dg-final { scan-assembler {\mpstd\M} } } */