From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 May 2020 13:54:34 +0000 (+0100)
Subject: clarifying comments
X-Git-Tag: div_pipeline~1321
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=212ad28798443d654f201e3e23c918564397062c;p=soc.git

clarifying comments
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 021ac8ab..e962692b 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -23,7 +23,9 @@ class ALUInputStage(PipeModBase):
         m = Module()
         comb = m.d.comb
 
+        ##### operand A #####
 
+        # operand a to be as-is or inverted
         a = Signal.like(self.i.a)
 
         with m.If(self.i.ctx.op.invert_a):
@@ -33,7 +35,7 @@ class ALUInputStage(PipeModBase):
 
         comb += self.o.a.eq(a)
 
-        # TODO: remove this because it's handled by the Computational Unit?
+        ##### operand B #####
 
         # If there's an immediate, set the B operand to that
         with m.If(self.i.ctx.op.imm_data.imm_ok):
@@ -41,6 +43,9 @@ class ALUInputStage(PipeModBase):
         with m.Else():
             comb += self.o.b.eq(self.i.b)
 
+        ##### carry-in #####
+
+        # either copy incoming carry or set to 1/0 as defined by op
         with m.Switch(self.i.ctx.op.input_carry):
             with m.Case(CryIn.ZERO):
                 comb += self.o.carry_in.eq(0)
@@ -49,6 +54,8 @@ class ALUInputStage(PipeModBase):
             with m.Case(CryIn.CA):
                 comb += self.o.carry_in.eq(self.i.carry_in)
 
+        ##### context #####
+
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m