From: Megan Wachs <megan@sifive.com>
Date: Tue, 25 Jul 2017 14:05:22 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2139ab0d98a72072d3ab6116ab55b9e90b26cabe;p=sifive-blocks.git

Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
---

2139ab0d98a72072d3ab6116ab55b9e90b26cabe
diff --cc src/main/scala/devices/uart/UARTPeriphery.scala
index d42850f,677394f..5564fef
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@@ -2,11 -2,10 +2,11 @@@
  package sifive.blocks.devices.uart
  
  import Chisel._
 +import chisel3.experimental.{withClockAndReset}
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 -import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 +import sifive.blocks.devices.pinctrl.{Pin}
  import sifive.blocks.util.ShiftRegisterInit
  
  case object PeripheryUARTKey extends Field[Seq[UARTParams]]