From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 29 Jul 2014 17:23:31 +0000 (+0200)
Subject: Bugfix in simlib.v for iverilog
X-Git-Tag: yosys-0.4~368
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2145e57ef08784484e875e64cb43b6d1f4dbe50c;p=yosys.git

Bugfix in simlib.v for iverilog
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 76aa4a52d..c2f6cb278 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -455,11 +455,12 @@ input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
 generate
-	if (B_SIGNED) begin:BLOCK1
-		assign Y = A[$signed(B) +: Y_WIDTH];
-	end else begin:BLOCK2
-		assign Y = A[B +: Y_WIDTH];
-	end
+	if (Y_WIDTH > 0)
+		if (B_SIGNED) begin:BLOCK1
+			assign Y = A[$signed(B) +: Y_WIDTH];
+		end else begin:BLOCK2
+			assign Y = A[B +: Y_WIDTH];
+		end
 endgenerate
 
 endmodule