From: Luke Kenneth Casson Leighton Date: Sun, 12 Jul 2020 03:46:04 +0000 (+0100) Subject: update-mode request write signalled too early X-Git-Tag: div_pipeline~84 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21466f48e229cc739552f8e26d718f32d3cb3c94;p=soc.git update-mode request write signalled too early --- diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 014ccbe0..c1f4f437 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -433,7 +433,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): op_is_ld & self.shadown_i) # request write of EA result only in update mode - comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update & + comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update & alu_valid & self.shadown_i) # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST