From: Michael Collison Date: Tue, 11 Jul 2017 00:17:02 +0000 (+0000) Subject: var_shift_mask_1.c: Fix for ILP32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=214f700a8bd18c37fc4a5390ccdee164d22443e2;p=gcc.git var_shift_mask_1.c: Fix for ILP32 2017-07-10 Michael Collison * gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32 From-SVN: r250112 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f6dec47d048..153da28e014 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-07-10 Michael Collison + + * gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32 + 2017-07-10 Uros Bizjak PR target/81375 diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c index e2b020ef3c4..0bd326a879d 100644 --- a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c +++ b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c @@ -11,17 +11,17 @@ f1 (unsigned x, int y) return x << (y & 31); } -unsigned long -f2 (unsigned long x, int y) +unsigned long long +f2 (unsigned long long x, int y) { return x << (y & 63); } -unsigned long -f3 (unsigned long bit_addr, int y) +unsigned long long +f3 (unsigned long long bit_addr, int y) { unsigned long bitnumb = bit_addr & 63; - return (1L << bitnumb); + return (1LL << bitnumb); } unsigned int @@ -31,28 +31,32 @@ f4 (unsigned int x, unsigned int y) return x >> y | (x << (32 - y)); } -unsigned long -f5 (unsigned long x, unsigned long y) +unsigned long long +f5 (unsigned long long x, unsigned long long y) { y &= 63; return x >> y | (x << (64 - y)); } -unsigned long -f6 (unsigned long x, unsigned long y) +unsigned int +f6 (unsigned int x, unsigned int y) { + return (x << (32 - (y & 31))); +} +unsigned long long +f7 (unsigned long long x, unsigned long long y) +{ return (x << (64 - (y & 63))); - } -unsigned long -f7 (unsigned long x, unsigned long y) +unsigned long long +f8 (unsigned long long x, unsigned long long y) { return (x << -(y & 63)); } -/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "lsl\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ /* { dg-final { scan-assembler-times "lsl\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 4 } } */ /* { dg-final { scan-assembler-times "ror\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 1 } } */ /* { dg-final { scan-assembler-times "ror\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */