From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 21:10:48 +0000 (-0600)
Subject: ARM: Reset simulation statistics when pref counters are reset.
X-Git-Tag: stable_2012_02_02~547
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2157b9976b55a6f3c25bbb788cdde931092aad3d;p=gem5.git

ARM: Reset simulation statistics when pref counters are reset.

The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean 'reset
the simulator statistics' instead.
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 649394270..4bdbe77ce 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -40,6 +40,7 @@
 
 #include "arch/arm/isa.hh"
 #include "sim/faults.hh"
+#include "sim/stat_control.hh"
 
 namespace ArmISA
 {
@@ -393,6 +394,18 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             warn("Not doing anything for write of miscreg ACTLR\n");
             break;
           case MISCREG_PMCR:
+            {
+              // Performance counters not implemented.  Instead, interpret
+              //   a reset command to this register to reset the simulator
+              //   statistics.
+              // PMCR_E | PMCR_P | PMCR_C
+              const int ResetAndEnableCounters = 0x7;
+              if (newVal == ResetAndEnableCounters) {
+                  inform("Resetting all simobject stats\n");
+                  Stats::schedStatEvent(false, true);
+                  break;
+              }
+            }
           case MISCREG_PMCCNTR:
           case MISCREG_PMSELR:
             warn("Not doing anything for write to miscreg %s\n",