From: Dave Airlie Date: Fri, 27 Aug 2010 05:45:58 +0000 (+1000) Subject: Revert "r600g: simplify states" X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2184f3ec3059eaf8a9a2b04c995162543f000862;p=mesa.git Revert "r600g: simplify states" This reverts commit bd25e23bf3740f59ce8859848c715daeb9e9821f. Apart from introducing a lot of hex magic numbers and being highly impenetable code, it causes lots of lockups on an average piglit run that always runs without lockups. Always run piglit before/after doing big things like this. --- diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index d3b722c82f7..72175fbbd5e 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx, unsigned srcx, unsigned srcy, unsigned srcz, unsigned width, unsigned height) { - util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz, + util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz, src, subsrc, srcx, srcy, srcz, width, height); } @@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600 memcpy(bo->data, vbo, 128); radeon_bo_unmap(rscreen->rw, bo); - rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0); + rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0); if (rstate == NULL) { radeon_bo_decref(rscreen->rw, bo); return -ENOMEM; @@ -199,35 +199,33 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600 /* set states (most default value are 0 and struct already * initialized to 0, thus avoid resetting them) */ - rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080; - rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000; - rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000; rstate->bo[0] = bo; rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; - rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID; - rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID; if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); return -ENOMEM; } bstates->vs_resource0 = rstate; - rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1); + rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1); if (rstate == NULL) { return -ENOMEM; } - rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010; - rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070; - rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000; - rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000; - rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000; + rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000; rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo); rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; @@ -305,7 +303,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree } radeon_bo_unmap(rscreen->rw, bo); - rstate = radeon_state(rscreen->rw, R600_VS_SHADER); + rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER); if (rstate == NULL) { radeon_bo_decref(rscreen->rw, bo); return NULL; @@ -323,8 +321,6 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree rstate->nbo = 2; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; - rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID; - rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID; if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); @@ -378,7 +374,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree } radeon_bo_unmap(rscreen->rw, bo); - rstate = radeon_state(rscreen->rw, R600_PS_SHADER); + rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER); if (rstate == NULL) { radeon_bo_decref(rscreen->rw, bo); return NULL; @@ -395,7 +391,6 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree rstate->bo[0] = bo; rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; - rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID; if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); @@ -408,7 +403,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen) { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_VGT); + rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT); if (rstate == NULL) return NULL; @@ -430,7 +425,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen) { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_DRAW); + rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW); if (rstate == NULL) return NULL; @@ -453,7 +448,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id); + rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id); if (rstate == NULL) return NULL; @@ -476,7 +471,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_RASTERIZER); + rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); if (rstate == NULL) return NULL; @@ -505,7 +500,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen) { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_DSA); + rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA); if (rstate == NULL) return NULL; @@ -529,7 +524,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen) { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_BLEND); + rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND); if (rstate == NULL) return NULL; @@ -548,7 +543,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen) { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_CB_CNTL); + rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL); if (rstate == NULL) return NULL; @@ -791,10 +786,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te r600_queries_suspend(ctx); /* schedule draw*/ - r = radeon_ctx_set_draw(rctx->ctx, draw); + r = radeon_ctx_set_draw_new(rctx->ctx, draw); if (r == -EBUSY) { r600_flush(ctx, 0, NULL); - r = radeon_ctx_set_draw(rctx->ctx, draw); + r = radeon_ctx_set_draw_new(rctx->ctx, draw); } if (r) { goto out; diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c index 790a85110bf..9af28356c5c 100644 --- a/src/gallium/drivers/r600/r600_context.c +++ b/src/gallium/drivers/r600/r600_context.c @@ -53,10 +53,12 @@ void r600_flush(struct pipe_context *ctx, unsigned flags, /* suspend queries */ r600_queries_suspend(ctx); + if (radeon_ctx_pm4(rctx->ctx)) + goto out; /* FIXME dumping should be removed once shader support instructions * without throwing bad code */ - if (!rctx->ctx->id) + if (!rctx->ctx->cpm4) goto out; sprintf(dname, "gallium-%08d.bof", dc); if (dc < 2) { @@ -71,7 +73,8 @@ void r600_flush(struct pipe_context *ctx, unsigned flags, } dc++; out: - radeon_ctx_clear(rctx->ctx); + rctx->ctx = radeon_ctx_decref(rctx->ctx); + rctx->ctx = radeon_ctx(rscreen->rw); /* resume queries */ r600_queries_resume(ctx); } @@ -215,7 +218,7 @@ static void r600_init_config(struct r600_context *rctx) num_es_stack_entries = 0; break; } - rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG); + rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG); rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000; switch (family) { diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c index a1a392ad2b5..1eb868c4c77 100644 --- a/src/gallium/drivers/r600/r600_draw.c +++ b/src/gallium/drivers/r600/r600_draw.c @@ -101,21 +101,19 @@ static int r600_draw_common(struct r600_draw *draw) rbuffer = (struct r600_resource*)vertex_buffer->buffer; offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset; format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format); - vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i); + vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i); if (vs_resource == NULL) return -ENOMEM; vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); vs_resource->nbo = 1; - vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID; - vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) | + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) | S_038008_DATA_FORMAT(format); - vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000; - vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000; + vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000; vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT; vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT; r = radeon_draw_set_new(rctx->draw, vs_resource); @@ -123,29 +121,22 @@ static int r600_draw_common(struct r600_draw *draw) return r; } /* FIXME start need to change winsys */ + draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW); + if (draw->draw == NULL) + return -ENOMEM; + draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count; + draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; if (draw->index_buffer) { - draw->draw = radeon_state(rscreen->rw, R600_DRAW); - if (draw->draw == NULL) - return -ENOMEM; - draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count; - draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator; rbuffer = (struct r600_resource*)draw->index_buffer; draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT; draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT; draw->draw->nbo = 1; - draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID; - } else { - draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO); - if (draw->draw == NULL) - return -ENOMEM; - draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count; - draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator; } r = radeon_draw_set_new(rctx->draw, draw->draw); if (r) return r; - draw->vgt = radeon_state(rscreen->rw, R600_VGT); + draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT); if (draw->vgt == NULL) return -ENOMEM; draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim; @@ -154,18 +145,23 @@ static int r600_draw_common(struct r600_draw *draw) draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start; draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000; draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type; + draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000; draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; + draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000; + draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000; r = radeon_draw_set_new(rctx->draw, draw->vgt); if (r) return r; /* FIXME */ - r = radeon_ctx_set_draw(rctx->ctx, rctx->draw); + r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw); if (r == -EBUSY) { r600_flush(draw->ctx, 0, NULL); - r = radeon_ctx_set_draw(rctx->ctx, rctx->draw); + r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw); } if (r) return r; + rctx->draw = radeon_draw_duplicate(rctx->draw); return 0; } diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 8b4fe8999f3..5929606cd28 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -36,11 +36,10 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r struct r600_screen *rscreen = rctx->screen; struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN); + rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN); if (rstate == NULL) return NULL; rstate->states[R600_QUERY__OFFSET] = rquery->num_results; - rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID; rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer); rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; @@ -56,11 +55,10 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60 struct r600_screen *rscreen = rctx->screen; struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_QUERY_END); + rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END); if (rstate == NULL) return NULL; rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8; - rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID; rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer); rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 052b4971f31..ebcf19c12b1 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta unsigned i, tmp; rpshader->rstate = radeon_state_decref(rpshader->rstate); - state = radeon_state(rscreen->rw, R600_VS_SHADER); + state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER); if (state == NULL) return -ENOMEM; for (i = 0; i < 10; i++) { @@ -152,8 +152,6 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta rpshader->rstate->nbo = 2; rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; - state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID; - state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID; return radeon_state_pm4(state); } @@ -168,7 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta rasterizer = &rctx->rasterizer->state.rasterizer; rpshader->rstate = radeon_state_decref(rpshader->rstate); - state = radeon_state(rscreen->rw, R600_PS_SHADER); + state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER); if (state == NULL) return -ENOMEM; for (i = 0; i < rshader->ninput; i++) { @@ -208,7 +206,6 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo); rpshader->rstate->nbo = 1; rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; - state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID; return radeon_state_pm4(state); } diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index e75575da792..b5e5346163c 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -283,17 +283,19 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, { struct r600_screen *rscreen = r600_screen(ctx->screen); struct r600_context *rctx = r600_context(ctx); - unsigned nconstant = 0, i, id; + unsigned nconstant = 0, i, type, id; struct radeon_state *rstate; struct pipe_transfer *transfer; u32 *ptr; switch (shader) { case PIPE_SHADER_VERTEX: - id = R600_VS_CONSTANT0; + id = R600_VS_CONSTANT; + type = R600_VS_CONSTANT_TYPE; break; case PIPE_SHADER_FRAGMENT: - id = R600_PS_CONSTANT0; + id = R600_PS_CONSTANT; + type = R600_PS_CONSTANT_TYPE; break; default: R600_ERR("unsupported %d\n", shader); @@ -305,7 +307,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx, if (ptr == NULL) return; for (i = 0; i < nconstant; i++) { - rstate = radeon_state(rscreen->rw, id + i); + rstate = radeon_state(rscreen->rw, type, id + i); if (rstate == NULL) return; rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0]; @@ -620,7 +622,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx) const struct pipe_blend_state *state = &rctx->blend->state.blend; int i; - rstate = radeon_state(rscreen->rw, R600_BLEND); + rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND); if (rstate == NULL) return NULL; rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]); @@ -679,14 +681,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip) struct radeon_state *rstate; const struct pipe_clip_state *state = &rctx->clip->state.clip; - rstate = radeon_state(rscreen->rw, R600_UCP0 + clip); + rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip); if (rstate == NULL) return NULL; - rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]); - rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]); - rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]); - rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]); + rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]); + rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]); + rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]); + rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]); if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); @@ -709,7 +711,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb) unsigned format, swap, ntype; const struct util_format_description *desc; - rstate = radeon_state(rscreen->rw, R600_CB0 + cb); + rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb); if (rstate == NULL) return NULL; rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; @@ -720,9 +722,6 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb) rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; rstate->placement[4] = RADEON_GEM_DOMAIN_GTT; - rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID; - rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID; - rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID; rstate->nbo = 3; pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1; @@ -741,14 +740,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb) S_0280A0_SOURCE_FORMAT(1) | S_0280A0_NUMBER_TYPE(ntype); - rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8; - rstate->states[R600_CB__CB_COLOR0_INFO] = color_info; - rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | + rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8; + rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info; + rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | S_028060_SLICE_TILE_MAX(slice); - rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000; - rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000; - rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000; - rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000; + rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000; if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); return NULL; @@ -769,7 +768,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx) if (state->zsbuf == NULL) return NULL; - rstate = radeon_state(rscreen->rw, R600_DB); + rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB); if (rstate == NULL) return NULL; @@ -783,7 +782,6 @@ static struct radeon_state *r600_db(struct r600_context *rctx) rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); rstate->nbo = 1; rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM; - rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID; level = state->zsbuf->level; pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1; slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1; @@ -846,7 +844,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx) prov_vtx = 0; rctx->flat_shade = state->flatshade; - rstate = radeon_state(rscreen->rw, R600_RASTERIZER); + rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER); if (rstate == NULL) return NULL; rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; @@ -927,7 +925,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx) } tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1); br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy); - rstate = radeon_state(rscreen->rw, R600_SCISSOR); + rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); if (rstate == NULL) return NULL; rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl; @@ -962,7 +960,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx) struct r600_screen *rscreen = rctx->screen; struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_VIEWPORT); + rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); if (rstate == NULL) return NULL; rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000; @@ -995,7 +993,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx) if (rctx->ps_shader == NULL) { return NULL; } - rstate = radeon_state(rscreen->rw, R600_DSA); + rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA); if (rstate == NULL) return NULL; @@ -1147,7 +1145,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx, struct r600_screen *rscreen = rctx->screen; struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, id); + rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id); if (rstate == NULL) return NULL; rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] = @@ -1248,7 +1246,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx, R600_ERR("unknow format %d\n", view->texture->format); return NULL; } - rstate = radeon_state(rscreen->rw, id); + rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id); if (rstate == NULL) { return NULL; } @@ -1270,36 +1268,34 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx, rstate->placement[1] = RADEON_GEM_DOMAIN_GTT; rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; rstate->placement[3] = RADEON_GEM_DOMAIN_GTT; - rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID; - rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID; pitch = (tmp->pitch[0] / tmp->bpt); pitch = (pitch + 0x7) & ~0x7; /* FIXME properly handle first level != 0 */ - rstate->states[R600_RESOURCE__RESOURCE_WORD0] = + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = S_038000_DIM(r600_tex_dim(view->texture->target)) | S_038000_TILE_MODE(array_mode) | S_038000_TILE_TYPE(tile_type) | S_038000_PITCH((pitch / 8) - 1) | S_038000_TEX_WIDTH(view->texture->width0 - 1); - rstate->states[R600_RESOURCE__RESOURCE_WORD1] = + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = S_038004_TEX_HEIGHT(view->texture->height0 - 1) | S_038004_TEX_DEPTH(view->texture->depth0 - 1) | S_038004_DATA_FORMAT(format); - rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8; - rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8; - rstate->states[R600_RESOURCE__RESOURCE_WORD4] = + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8; + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) | S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) | S_038010_REQUEST_SIZE(1) | S_038010_BASE_LEVEL(view->first_level); - rstate->states[R600_RESOURCE__RESOURCE_WORD5] = + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = S_038014_LAST_LEVEL(view->last_level) | S_038014_BASE_ARRAY(0) | S_038014_LAST_ARRAY(0); - rstate->states[R600_RESOURCE__RESOURCE_WORD6] = + rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE); if (radeon_state_pm4(rstate)) { radeon_state_decref(rstate); @@ -1346,7 +1342,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx) target_mask |= (pbs->rt[0].colormask << (4 * i)); } } - rstate = radeon_state(rscreen->rw, R600_CB_CNTL); + rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL); rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask; rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask; rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control; @@ -1423,7 +1419,7 @@ int r600_context_hw_states(struct pipe_context *ctx) if (rctx->ps_sampler[i]) { rctx->hw_states.ps_sampler[i] = r600_sampler(rctx, &rctx->ps_sampler[i]->state.sampler, - R600_PS_SAMPLER0 + i); + R600_PS_SAMPLER + i); } } rctx->hw_states.ps_nsampler = rctx->ps_nsampler; @@ -1431,7 +1427,7 @@ int r600_context_hw_states(struct pipe_context *ctx) if (rctx->ps_sampler_view[i]) { rctx->hw_states.ps_resource[i] = r600_resource(ctx, &rctx->ps_sampler_view[i]->state.sampler_view, - R600_PS_RESOURCE0 + i); + R600_PS_RESOURCE + i); } } rctx->hw_states.ps_nresource = rctx->ps_nsampler_view; diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 9dc0208eb13..fb84ed9cfea 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_SCISSOR); + rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR); if (rstate == NULL) return NULL; @@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen, unsigned format, swap, ntype; const struct util_format_description *desc; - rstate = radeon_state(rscreen->rw, R600_CB0); + rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0); if (rstate == NULL) return NULL; rbuffer = &rtexture->resource; @@ -742,16 +742,13 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen, rstate->nbo = 3; color_info = S_0280A0_SOURCE_FORMAT(1); } - rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID; - rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID; - rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID; color_info |= S_0280A0_FORMAT(format) | S_0280A0_COMP_SWAP(swap) | S_0280A0_BLEND_CLAMP(1) | S_0280A0_NUMBER_TYPE(ntype); - rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8; - rstate->states[R600_CB__CB_COLOR0_INFO] = color_info; - rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | + rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8; + rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info; + rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) | S_028060_SLICE_TILE_MAX(slice); if (radeon_state_pm4(rstate)) { @@ -769,7 +766,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource *rbuffer; unsigned pitch, slice, format; - rstate = radeon_state(rscreen->rw, R600_DB); + rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB); if (rstate == NULL) return NULL; rbuffer = &rtexture->resource; @@ -787,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen, rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1; rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); - rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID; rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo); rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; rstate->nbo = 1; @@ -819,7 +815,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr { struct radeon_state *rstate; - rstate = radeon_state(rscreen->rw, R600_VIEWPORT); + rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT); if (rstate == NULL) return NULL; diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h index 777fe3e7922..b2cc74f6967 100644 --- a/src/gallium/drivers/r600/radeon.h +++ b/src/gallium/drivers/r600/radeon.h @@ -104,18 +104,26 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo); struct radeon_state { struct radeon *radeon; unsigned refcount; + unsigned type; unsigned id; + unsigned nstates; + u32 *states; + unsigned npm4; unsigned cpm4; - u32 states[128]; u32 pm4_crc; + u32 *pm4; + u32 nimmd; + u32 *immd; unsigned nbo; struct radeon_bo *bo[4]; - unsigned reloc_pm4_id[4]; + unsigned nreloc; + unsigned reloc_pm4_id[8]; + unsigned reloc_bo_id[8]; u32 placement[8]; unsigned bo_dirty[4]; }; -struct radeon_state *radeon_state(struct radeon *radeon, u32 id); +struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id); struct radeon_state *radeon_state_incref(struct radeon_state *state); struct radeon_state *radeon_state_decref(struct radeon_state *state); int radeon_state_pm4(struct radeon_state *state); @@ -139,6 +147,16 @@ int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state); int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state); int radeon_draw_check(struct radeon_draw *draw); +struct radeon_ctx *radeon_ctx(struct radeon *radeon); +struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx); +struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx); +int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state); +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); +int radeon_ctx_pm4(struct radeon_ctx *ctx); +int radeon_ctx_submit(struct radeon_ctx *ctx); +void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); + /* * radeon context functions */ @@ -151,216 +169,261 @@ struct radeon_cs_reloc { }; #pragma pack() -struct radeon_ctx_bo { - struct radeon_bo *bo; - u32 bo_flushed; - unsigned state_id; -}; - struct radeon_ctx { int refcount; struct radeon *radeon; u32 *pm4; - int npm4; + u32 cpm4; + u32 draw_cpm4; unsigned id; + unsigned next_id; unsigned nreloc; - unsigned max_reloc; struct radeon_cs_reloc *reloc; unsigned nbo; - struct radeon_ctx_bo *bo; - unsigned max_bo; - u32 *state_crc32; + struct radeon_bo **bo; + unsigned ndraw; + struct radeon_draw *cdraw; + struct radeon_draw **draw; + unsigned nstate; + struct radeon_state **state; }; -struct radeon_ctx *radeon_ctx(struct radeon *radeon); -struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx); -struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx); -void radeon_ctx_clear(struct radeon_ctx *ctx); -int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw); -int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state); -int radeon_ctx_pm4(struct radeon_ctx *ctx); -int radeon_ctx_submit(struct radeon_ctx *ctx); -void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); - - /* * R600/R700 */ -#define R600_CONFIG 0 -#define R600_CB_CNTL 1 -#define R600_RASTERIZER 2 -#define R600_VIEWPORT 3 -#define R600_SCISSOR 4 -#define R600_BLEND 5 -#define R600_DSA 6 -#define R600_VGT 7 -#define R600_QUERY_BEGIN 8 -#define R600_QUERY_END 9 -#define R600_VS_SHADER 10 -#define R600_PS_SHADER 11 -#define R600_DB 12 -#define R600_CB0 13 -#define R600_UCP0 21 -#define R600_PS_RESOURCE0 27 -#define R600_VS_RESOURCE0 187 -#define R600_FS_RESOURCE0 347 -#define R600_GS_RESOURCE0 363 -#define R600_PS_CONSTANT0 523 -#define R600_VS_CONSTANT0 779 -#define R600_PS_SAMPLER0 1035 -#define R600_VS_SAMPLER0 1053 -#define R600_GS_SAMPLER0 1071 -#define R600_PS_SAMPLER_BORDER0 1089 -#define R600_VS_SAMPLER_BORDER0 1107 -#define R600_GS_SAMPLER_BORDER0 1125 -#define R600_DRAW_AUTO 1143 -#define R600_DRAW 1144 -#define R600_NSTATE 1145 + +#define R600_NSTATE 1288 +#define R600_NTYPE 35 + +#define R600_CONFIG 0 +#define R600_CONFIG_TYPE 0 +#define R600_CB_CNTL 1 +#define R600_CB_CNTL_TYPE 1 +#define R600_RASTERIZER 2 +#define R600_RASTERIZER_TYPE 2 +#define R600_VIEWPORT 3 +#define R600_VIEWPORT_TYPE 3 +#define R600_SCISSOR 4 +#define R600_SCISSOR_TYPE 4 +#define R600_BLEND 5 +#define R600_BLEND_TYPE 5 +#define R600_DSA 6 +#define R600_DSA_TYPE 6 +#define R600_VS_SHADER 7 +#define R600_VS_SHADER_TYPE 7 +#define R600_PS_SHADER 8 +#define R600_PS_SHADER_TYPE 8 +#define R600_PS_CONSTANT 9 +#define R600_PS_CONSTANT_TYPE 9 +#define R600_VS_CONSTANT 265 +#define R600_VS_CONSTANT_TYPE 10 +#define R600_PS_RESOURCE 521 +#define R600_PS_RESOURCE_TYPE 11 +#define R600_VS_RESOURCE 681 +#define R600_VS_RESOURCE_TYPE 12 +#define R600_FS_RESOURCE 841 +#define R600_FS_RESOURCE_TYPE 13 +#define R600_GS_RESOURCE 1001 +#define R600_GS_RESOURCE_TYPE 14 +#define R600_PS_SAMPLER 1161 +#define R600_PS_SAMPLER_TYPE 15 +#define R600_VS_SAMPLER 1179 +#define R600_VS_SAMPLER_TYPE 16 +#define R600_GS_SAMPLER 1197 +#define R600_GS_SAMPLER_TYPE 17 +#define R600_PS_SAMPLER_BORDER 1215 +#define R600_PS_SAMPLER_BORDER_TYPE 18 +#define R600_VS_SAMPLER_BORDER 1233 +#define R600_VS_SAMPLER_BORDER_TYPE 19 +#define R600_GS_SAMPLER_BORDER 1251 +#define R600_GS_SAMPLER_BORDER_TYPE 20 +#define R600_CB0 1269 +#define R600_CB0_TYPE 21 +#define R600_CB1 1270 +#define R600_CB1_TYPE 22 +#define R600_CB2 1271 +#define R600_CB2_TYPE 23 +#define R600_CB3 1272 +#define R600_CB3_TYPE 24 +#define R600_CB4 1273 +#define R600_CB4_TYPE 25 +#define R600_CB5 1274 +#define R600_CB5_TYPE 26 +#define R600_CB6 1275 +#define R600_CB6_TYPE 27 +#define R600_CB7 1276 +#define R600_CB7_TYPE 28 +#define R600_QUERY_BEGIN 1277 +#define R600_QUERY_BEGIN_TYPE 29 +#define R600_QUERY_END 1278 +#define R600_QUERY_END_TYPE 30 +#define R600_DB 1279 +#define R600_DB_TYPE 31 +#define R600_CLIP 1280 +#define R600_CLIP_TYPE 32 +#define R600_VGT 1286 +#define R600_VGT_TYPE 33 +#define R600_DRAW 1287 +#define R600_DRAW_TYPE 34 /* R600_CONFIG */ -#define R600_CONFIG__SQ_CONFIG 0 +#define R600_CONFIG__SQ_CONFIG 0 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1 1 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2 2 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT 3 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1 4 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2 5 -#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 8 -#define R600_CONFIG__TA_CNTL_AUX 11 -#define R600_CONFIG__VC_ENHANCE 14 -#define R600_CONFIG__DB_DEBUG 17 -#define R600_CONFIG__DB_WATERMARKS 20 -#define R600_CONFIG__SX_MISC 23 -#define R600_CONFIG__SPI_THREAD_GROUPING 26 -#define R600_CONFIG__CB_SHADER_CONTROL 29 -#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 32 -#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 33 -#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 34 -#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 35 -#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 36 -#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 37 -#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 38 -#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 39 -#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 40 -#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 43 -#define R600_CONFIG__VGT_HOS_CNTL 44 -#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 45 -#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 46 -#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 47 -#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 48 -#define R600_CONFIG__VGT_GROUP_FIRST_DECR 49 -#define R600_CONFIG__VGT_GROUP_DECR 50 -#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 51 -#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 52 -#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 53 -#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 54 -#define R600_CONFIG__VGT_GS_MODE 55 -#define R600_CONFIG__PA_SC_MODE_CNTL 58 -#define R600_CONFIG__VGT_STRMOUT_EN 61 -#define R600_CONFIG__VGT_REUSE_OFF 62 -#define R600_CONFIG__VGT_VTX_CNT_EN 63 -#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 66 +#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 6 +#define R600_CONFIG__TA_CNTL_AUX 7 +#define R600_CONFIG__VC_ENHANCE 8 +#define R600_CONFIG__DB_DEBUG 9 +#define R600_CONFIG__DB_WATERMARKS 10 +#define R600_CONFIG__SX_MISC 11 +#define R600_CONFIG__SPI_THREAD_GROUPING 12 +#define R600_CONFIG__CB_SHADER_CONTROL 13 +#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE 14 +#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE 15 +#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE 16 +#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE 17 +#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE 18 +#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE 19 +#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE 20 +#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE 21 +#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE 22 +#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL 23 +#define R600_CONFIG__VGT_HOS_CNTL 24 +#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL 25 +#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL 26 +#define R600_CONFIG__VGT_HOS_REUSE_DEPTH 27 +#define R600_CONFIG__VGT_GROUP_PRIM_TYPE 28 +#define R600_CONFIG__VGT_GROUP_FIRST_DECR 29 +#define R600_CONFIG__VGT_GROUP_DECR 30 +#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL 31 +#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL 32 +#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 33 +#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 34 +#define R600_CONFIG__VGT_GS_MODE 35 +#define R600_CONFIG__PA_SC_MODE_CNTL 36 +#define R600_CONFIG__VGT_STRMOUT_EN 37 +#define R600_CONFIG__VGT_REUSE_OFF 38 +#define R600_CONFIG__VGT_VTX_CNT_EN 39 +#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN 40 +#define R600_CONFIG_SIZE 41 +#define R600_CONFIG_PM4 128 /* R600_CB_CNTL */ -#define R600_CB_CNTL__CB_CLEAR_RED 0 -#define R600_CB_CNTL__CB_CLEAR_GREEN 1 -#define R600_CB_CNTL__CB_CLEAR_BLUE 2 -#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 -#define R600_CB_CNTL__CB_SHADER_MASK 6 -#define R600_CB_CNTL__CB_TARGET_MASK 7 -#define R600_CB_CNTL__CB_FOG_RED 10 -#define R600_CB_CNTL__CB_FOG_GREEN 11 -#define R600_CB_CNTL__CB_FOG_BLUE 12 -#define R600_CB_CNTL__CB_COLOR_CONTROL 15 -#define R600_CB_CNTL__PA_SC_AA_CONFIG 18 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 21 -#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 22 -#define R600_CB_CNTL__CB_CLRCMP_CONTROL 25 -#define R600_CB_CNTL__CB_CLRCMP_SRC 26 -#define R600_CB_CNTL__CB_CLRCMP_DST 27 -#define R600_CB_CNTL__CB_CLRCMP_MSK 28 -#define R600_CB_CNTL__PA_SC_AA_MASK 31 +#define R600_CB_CNTL__CB_CLEAR_RED 0 +#define R600_CB_CNTL__CB_CLEAR_GREEN 1 +#define R600_CB_CNTL__CB_CLEAR_BLUE 2 +#define R600_CB_CNTL__CB_CLEAR_ALPHA 3 +#define R600_CB_CNTL__CB_SHADER_MASK 4 +#define R600_CB_CNTL__CB_TARGET_MASK 5 +#define R600_CB_CNTL__CB_FOG_RED 6 +#define R600_CB_CNTL__CB_FOG_GREEN 7 +#define R600_CB_CNTL__CB_FOG_BLUE 8 +#define R600_CB_CNTL__CB_COLOR_CONTROL 9 +#define R600_CB_CNTL__PA_SC_AA_CONFIG 10 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 11 +#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 12 +#define R600_CB_CNTL__CB_CLRCMP_CONTROL 13 +#define R600_CB_CNTL__CB_CLRCMP_SRC 14 +#define R600_CB_CNTL__CB_CLRCMP_DST 15 +#define R600_CB_CNTL__CB_CLRCMP_MSK 16 +#define R600_CB_CNTL__PA_SC_AA_MASK 17 +#define R600_CB_CNTL_SIZE 18 +#define R600_CB_CNTL_PM4 128 /* R600_RASTERIZER */ #define R600_RASTERIZER__SPI_INTERP_CONTROL_0 0 -#define R600_RASTERIZER__PA_CL_CLIP_CNTL 3 -#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 4 -#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 7 -#define R600_RASTERIZER__PA_CL_NANINF_CNTL 8 -#define R600_RASTERIZER__PA_SU_POINT_SIZE 11 -#define R600_RASTERIZER__PA_SU_POINT_MINMAX 12 -#define R600_RASTERIZER__PA_SU_LINE_CNTL 13 -#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 14 -#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 17 -#define R600_RASTERIZER__PA_SC_LINE_CNTL 20 -#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 23 -#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 24 -#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 25 -#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 26 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 29 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 30 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 31 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 32 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 33 -#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 34 +#define R600_RASTERIZER__PA_CL_CLIP_CNTL 1 +#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL 2 +#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL 3 +#define R600_RASTERIZER__PA_CL_NANINF_CNTL 4 +#define R600_RASTERIZER__PA_SU_POINT_SIZE 5 +#define R600_RASTERIZER__PA_SU_POINT_MINMAX 6 +#define R600_RASTERIZER__PA_SU_LINE_CNTL 7 +#define R600_RASTERIZER__PA_SC_LINE_STIPPLE 8 +#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL 9 +#define R600_RASTERIZER__PA_SC_LINE_CNTL 10 +#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11 +#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12 +#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13 +#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19 +#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20 +#define R600_RASTERIZER_SIZE 21 +#define R600_RASTERIZER_PM4 128 /* R600_VIEWPORT */ #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0 0 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0 1 -#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 4 -#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 7 -#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 10 -#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 13 -#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 16 -#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 19 -#define R600_VIEWPORT__PA_CL_VTE_CNTL 22 +#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0 2 +#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0 3 +#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4 +#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5 +#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6 +#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7 +#define R600_VIEWPORT__PA_CL_VTE_CNTL 8 +#define R600_VIEWPORT_SIZE 9 +#define R600_VIEWPORT_PM4 128 /* R600_SCISSOR */ #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1 -#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 4 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 5 -#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 6 -#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 7 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 8 -#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 9 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 10 -#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 11 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 12 -#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 13 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 14 -#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 15 -#define R600_SCISSOR__PA_SC_EDGERULE 16 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 19 -#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 20 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 23 -#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 24 +#define R600_SCISSOR__PA_SC_WINDOW_OFFSET 2 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3 +#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4 +#define R600_SCISSOR__PA_SC_CLIPRECT_RULE 5 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL 6 +#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR 7 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL 8 +#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR 9 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL 10 +#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR 11 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL 12 +#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR 13 +#define R600_SCISSOR__PA_SC_EDGERULE 14 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15 +#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17 +#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18 +#define R600_SCISSOR_SIZE 19 +#define R600_SCISSOR_PM4 128 /* R600_BLEND */ -#define R600_BLEND__CB_BLEND_RED 0 -#define R600_BLEND__CB_BLEND_GREEN 1 -#define R600_BLEND__CB_BLEND_BLUE 2 -#define R600_BLEND__CB_BLEND_ALPHA 3 -#define R600_BLEND__CB_BLEND0_CONTROL 6 -#define R600_BLEND__CB_BLEND1_CONTROL 7 -#define R600_BLEND__CB_BLEND2_CONTROL 8 -#define R600_BLEND__CB_BLEND3_CONTROL 9 -#define R600_BLEND__CB_BLEND4_CONTROL 10 -#define R600_BLEND__CB_BLEND5_CONTROL 11 -#define R600_BLEND__CB_BLEND6_CONTROL 12 -#define R600_BLEND__CB_BLEND7_CONTROL 13 -#define R600_BLEND__CB_BLEND_CONTROL 16 +#define R600_BLEND__CB_BLEND_RED 0 +#define R600_BLEND__CB_BLEND_GREEN 1 +#define R600_BLEND__CB_BLEND_BLUE 2 +#define R600_BLEND__CB_BLEND_ALPHA 3 +#define R600_BLEND__CB_BLEND0_CONTROL 4 +#define R600_BLEND__CB_BLEND1_CONTROL 5 +#define R600_BLEND__CB_BLEND2_CONTROL 6 +#define R600_BLEND__CB_BLEND3_CONTROL 7 +#define R600_BLEND__CB_BLEND4_CONTROL 8 +#define R600_BLEND__CB_BLEND5_CONTROL 9 +#define R600_BLEND__CB_BLEND6_CONTROL 10 +#define R600_BLEND__CB_BLEND7_CONTROL 11 +#define R600_BLEND__CB_BLEND_CONTROL 12 +#define R600_BLEND_SIZE 13 +#define R600_BLEND_PM4 128 /* R600_DSA */ -#define R600_DSA__DB_STENCIL_CLEAR 0 -#define R600_DSA__DB_DEPTH_CLEAR 1 -#define R600_DSA__SX_ALPHA_TEST_CONTROL 4 -#define R600_DSA__DB_STENCILREFMASK 7 -#define R600_DSA__DB_STENCILREFMASK_BF 8 -#define R600_DSA__SX_ALPHA_REF 9 -#define R600_DSA__SPI_FOG_FUNC_SCALE 12 -#define R600_DSA__SPI_FOG_FUNC_BIAS 13 -#define R600_DSA__SPI_FOG_CNTL 16 -#define R600_DSA__DB_DEPTH_CONTROL 19 -#define R600_DSA__DB_SHADER_CONTROL 22 -#define R600_DSA__DB_RENDER_CONTROL 25 -#define R600_DSA__DB_RENDER_OVERRIDE 26 -#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 29 -#define R600_DSA__DB_PRELOAD_CONTROL 30 -#define R600_DSA__DB_ALPHA_TO_MASK 33 +#define R600_DSA__DB_STENCIL_CLEAR 0 +#define R600_DSA__DB_DEPTH_CLEAR 1 +#define R600_DSA__SX_ALPHA_TEST_CONTROL 2 +#define R600_DSA__DB_STENCILREFMASK 3 +#define R600_DSA__DB_STENCILREFMASK_BF 4 +#define R600_DSA__SX_ALPHA_REF 5 +#define R600_DSA__SPI_FOG_FUNC_SCALE 6 +#define R600_DSA__SPI_FOG_FUNC_BIAS 7 +#define R600_DSA__SPI_FOG_CNTL 8 +#define R600_DSA__DB_DEPTH_CONTROL 9 +#define R600_DSA__DB_SHADER_CONTROL 10 +#define R600_DSA__DB_RENDER_CONTROL 11 +#define R600_DSA__DB_RENDER_OVERRIDE 12 +#define R600_DSA__DB_SRESULTS_COMPARE_STATE1 13 +#define R600_DSA__DB_PRELOAD_CONTROL 14 +#define R600_DSA__DB_ALPHA_TO_MASK 15 +#define R600_DSA_SIZE 16 +#define R600_DSA_PM4 128 /* R600_VS_SHADER */ #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0 0 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1 1 @@ -394,25 +457,25 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29 29 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30 30 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31 31 -#define R600_VS_SHADER__SPI_VS_OUT_ID_0 34 -#define R600_VS_SHADER__SPI_VS_OUT_ID_1 35 -#define R600_VS_SHADER__SPI_VS_OUT_ID_2 36 -#define R600_VS_SHADER__SPI_VS_OUT_ID_3 37 -#define R600_VS_SHADER__SPI_VS_OUT_ID_4 38 -#define R600_VS_SHADER__SPI_VS_OUT_ID_5 39 -#define R600_VS_SHADER__SPI_VS_OUT_ID_6 40 -#define R600_VS_SHADER__SPI_VS_OUT_ID_7 41 -#define R600_VS_SHADER__SPI_VS_OUT_ID_8 42 -#define R600_VS_SHADER__SPI_VS_OUT_ID_9 43 -#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 46 -#define R600_VS_SHADER__SQ_PGM_START_VS 49 -#define R600_VS_SHADER__SQ_PGM_START_VS_BO_ID 51 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 54 -#define R600_VS_SHADER__SQ_PGM_START_FS 57 -#define R600_VS_SHADER__SQ_PGM_START_FS_BO_ID 59 -#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 62 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 65 -#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 68 +#define R600_VS_SHADER__SPI_VS_OUT_ID_0 32 +#define R600_VS_SHADER__SPI_VS_OUT_ID_1 33 +#define R600_VS_SHADER__SPI_VS_OUT_ID_2 34 +#define R600_VS_SHADER__SPI_VS_OUT_ID_3 35 +#define R600_VS_SHADER__SPI_VS_OUT_ID_4 36 +#define R600_VS_SHADER__SPI_VS_OUT_ID_5 37 +#define R600_VS_SHADER__SPI_VS_OUT_ID_6 38 +#define R600_VS_SHADER__SPI_VS_OUT_ID_7 39 +#define R600_VS_SHADER__SPI_VS_OUT_ID_8 40 +#define R600_VS_SHADER__SPI_VS_OUT_ID_9 41 +#define R600_VS_SHADER__SPI_VS_OUT_CONFIG 42 +#define R600_VS_SHADER__SQ_PGM_START_VS 43 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS 44 +#define R600_VS_SHADER__SQ_PGM_START_FS 45 +#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS 46 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS 47 +#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS 48 +#define R600_VS_SHADER_SIZE 49 +#define R600_VS_SHADER_PM4 128 /* R600_PS_SHADER */ #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 0 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1 1 @@ -446,104 +509,158 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file); #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29 29 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30 30 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31 31 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 34 -#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 35 -#define R600_PS_SHADER__SPI_INPUT_Z 38 -#define R600_PS_SHADER__SQ_PGM_START_PS 41 -#define R600_PS_SHADER__SQ_PGM_START_PS_BO_ID 43 -#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 46 -#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 47 -#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 50 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0 32 +#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1 33 +#define R600_PS_SHADER__SPI_INPUT_Z 34 +#define R600_PS_SHADER__SQ_PGM_START_PS 35 +#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS 36 +#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS 37 +#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS 38 +#define R600_PS_SHADER_SIZE 39 +#define R600_PS_SHADER_PM4 128 /* R600_PS_CONSTANT */ #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0 0 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0 1 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0 2 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0 3 +#define R600_PS_CONSTANT_SIZE 4 +#define R600_PS_CONSTANT_PM4 128 /* R600_VS_CONSTANT */ #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256 0 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256 1 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256 2 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256 3 +#define R600_VS_CONSTANT_SIZE 4 +#define R600_VS_CONSTANT_PM4 128 /* R600_PS_RESOURCE */ -#define R600_RESOURCE__RESOURCE_WORD0 0 -#define R600_RESOURCE__RESOURCE_WORD1 1 -#define R600_RESOURCE__RESOURCE_WORD2 2 -#define R600_RESOURCE__RESOURCE_WORD3 3 -#define R600_RESOURCE__RESOURCE_WORD4 4 -#define R600_RESOURCE__RESOURCE_WORD5 5 -#define R600_RESOURCE__RESOURCE_WORD6 6 -#define R600_RESOURCE__RESOURCE_BO0_ID 8 -#define R600_RESOURCE__RESOURCE_BO1_ID 10 +#define R600_PS_RESOURCE__RESOURCE0_WORD0 0 +#define R600_PS_RESOURCE__RESOURCE0_WORD1 1 +#define R600_PS_RESOURCE__RESOURCE0_WORD2 2 +#define R600_PS_RESOURCE__RESOURCE0_WORD3 3 +#define R600_PS_RESOURCE__RESOURCE0_WORD4 4 +#define R600_PS_RESOURCE__RESOURCE0_WORD5 5 +#define R600_PS_RESOURCE__RESOURCE0_WORD6 6 +#define R600_PS_RESOURCE_SIZE 7 +#define R600_PS_RESOURCE_PM4 128 +/* R600_VS_RESOURCE */ +#define R600_VS_RESOURCE__RESOURCE160_WORD0 0 +#define R600_VS_RESOURCE__RESOURCE160_WORD1 1 +#define R600_VS_RESOURCE__RESOURCE160_WORD2 2 +#define R600_VS_RESOURCE__RESOURCE160_WORD3 3 +#define R600_VS_RESOURCE__RESOURCE160_WORD4 4 +#define R600_VS_RESOURCE__RESOURCE160_WORD5 5 +#define R600_VS_RESOURCE__RESOURCE160_WORD6 6 +#define R600_VS_RESOURCE_SIZE 7 +#define R600_VS_RESOURCE_PM4 128 +/* R600_FS_RESOURCE */ +#define R600_FS_RESOURCE__RESOURCE320_WORD0 0 +#define R600_FS_RESOURCE__RESOURCE320_WORD1 1 +#define R600_FS_RESOURCE__RESOURCE320_WORD2 2 +#define R600_FS_RESOURCE__RESOURCE320_WORD3 3 +#define R600_FS_RESOURCE__RESOURCE320_WORD4 4 +#define R600_FS_RESOURCE__RESOURCE320_WORD5 5 +#define R600_FS_RESOURCE__RESOURCE320_WORD6 6 +#define R600_FS_RESOURCE_SIZE 7 +#define R600_FS_RESOURCE_PM4 128 +/* R600_GS_RESOURCE */ +#define R600_GS_RESOURCE__RESOURCE336_WORD0 0 +#define R600_GS_RESOURCE__RESOURCE336_WORD1 1 +#define R600_GS_RESOURCE__RESOURCE336_WORD2 2 +#define R600_GS_RESOURCE__RESOURCE336_WORD3 3 +#define R600_GS_RESOURCE__RESOURCE336_WORD4 4 +#define R600_GS_RESOURCE__RESOURCE336_WORD5 5 +#define R600_GS_RESOURCE__RESOURCE336_WORD6 6 +#define R600_GS_RESOURCE_SIZE 7 +#define R600_GS_RESOURCE_PM4 128 /* R600_PS_SAMPLER */ #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2 +#define R600_PS_SAMPLER_SIZE 3 +#define R600_PS_SAMPLER_PM4 128 /* R600_VS_SAMPLER */ -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 -#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1 +#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2 +#define R600_VS_SAMPLER_SIZE 3 +#define R600_VS_SAMPLER_PM4 128 /* R600_GS_SAMPLER */ -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 -#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1 +#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2 +#define R600_GS_SAMPLER_SIZE 3 +#define R600_GS_SAMPLER_PM4 128 /* R600_PS_SAMPLER_BORDER */ -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 -#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 0 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 1 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 2 +#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 3 +#define R600_PS_SAMPLER_BORDER_SIZE 4 +#define R600_PS_SAMPLER_BORDER_PM4 128 /* R600_VS_SAMPLER_BORDER */ -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 -#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 0 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 1 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 2 +#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 3 +#define R600_VS_SAMPLER_BORDER_SIZE 4 +#define R600_VS_SAMPLER_BORDER_PM4 128 /* R600_GS_SAMPLER_BORDER */ -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 -#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 -/* R600_CB */ -#define R600_CB__CB_COLOR0_BASE 0 -#define R600_CB__CB_COLOR0_BASE_BO_ID 2 -#define R600_CB__CB_COLOR0_INFO 5 -#define R600_CB__CB_COLOR0_SIZE 8 -#define R600_CB__CB_COLOR0_VIEW 11 -#define R600_CB__CB_COLOR0_FRAG 14 -#define R600_CB__CB_COLOR0_FRAG_BO_ID 16 -#define R600_CB__CB_COLOR0_TILE 19 -#define R600_CB__CB_COLOR0_TILE_BO_ID 21 -#define R600_CB__CB_COLOR0_MASK 24 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 0 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 1 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 2 +#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 3 +#define R600_GS_SAMPLER_BORDER_SIZE 4 +#define R600_GS_SAMPLER_BORDER_PM4 128 +/* R600_CB0 */ +#define R600_CB0__CB_COLOR0_BASE 0 +#define R600_CB0__CB_COLOR0_INFO 1 +#define R600_CB0__CB_COLOR0_SIZE 2 +#define R600_CB0__CB_COLOR0_VIEW 3 +#define R600_CB0__CB_COLOR0_FRAG 4 +#define R600_CB0__CB_COLOR0_TILE 5 +#define R600_CB0__CB_COLOR0_MASK 6 +#define R600_CB0_SIZE 7 +#define R600_CB0_PM4 128 /* R600_DB */ -#define R600_DB__DB_DEPTH_BASE 0 -#define R600_DB__DB_DEPTH_BASE_BO_ID 2 -#define R600_DB__DB_DEPTH_SIZE 5 -#define R600_DB__DB_DEPTH_VIEW 6 -#define R600_DB__DB_DEPTH_INFO 9 -#define R600_DB__DB_HTILE_SURFACE 12 -#define R600_DB__DB_PREFETCH_LIMIT 15 +#define R600_DB__DB_DEPTH_BASE 0 +#define R600_DB__DB_DEPTH_SIZE 1 +#define R600_DB__DB_DEPTH_VIEW 2 +#define R600_DB__DB_DEPTH_INFO 3 +#define R600_DB__DB_HTILE_SURFACE 4 +#define R600_DB__DB_PREFETCH_LIMIT 5 +#define R600_DB_SIZE 6 +#define R600_DB_PM4 128 /* R600_VGT */ -#define R600_VGT__VGT_MAX_VTX_INDX 0 -#define R600_VGT__VGT_MIN_VTX_INDX 1 -#define R600_VGT__VGT_INDX_OFFSET 2 -#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 3 -#define R600_VGT__VGT_PRIMITIVE_TYPE 6 -#define R600_VGT__VGT_DMA_INDEX_TYPE 8 -#define R600_VGT__VGT_DMA_NUM_INSTANCES 10 -/* R600_DRAW_AUTO */ -#define R600_DRAW_AUTO__VGT_NUM_INDICES 0 -#define R600_DRAW_AUTO__VGT_DRAW_INITIATOR 1 +#define R600_VGT__VGT_PRIMITIVE_TYPE 0 +#define R600_VGT__VGT_MAX_VTX_INDX 1 +#define R600_VGT__VGT_MIN_VTX_INDX 2 +#define R600_VGT__VGT_INDX_OFFSET 3 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX 4 +#define R600_VGT__VGT_DMA_INDEX_TYPE 5 +#define R600_VGT__VGT_PRIMITIVEID_EN 6 +#define R600_VGT__VGT_DMA_NUM_INSTANCES 7 +#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN 8 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_0 9 +#define R600_VGT__VGT_INSTANCE_STEP_RATE_1 10 +#define R600_VGT_SIZE 11 +#define R600_VGT_PM4 128 /* R600_DRAW */ -#define R600_DRAW__VGT_DMA_BASE 0 -#define R600_DRAW__VGT_DMA_BASE_HI 1 -#define R600_DRAW__VGT_NUM_INDICES 2 -#define R600_DRAW__VGT_DRAW_INITIATOR 3 -#define R600_DRAW__INDICES_BO_ID 5 -/* R600_UCP */ -#define R600_UCP__PA_CL_UCP_X_0 0 -#define R600_UCP__PA_CL_UCP_Y_0 1 -#define R600_UCP__PA_CL_UCP_Z_0 2 -#define R600_UCP__PA_CL_UCP_W_0 3 +#define R600_DRAW__VGT_NUM_INDICES 0 +#define R600_DRAW__VGT_DMA_BASE_HI 1 +#define R600_DRAW__VGT_DMA_BASE 2 +#define R600_DRAW__VGT_DRAW_INITIATOR 3 +#define R600_DRAW_SIZE 4 +#define R600_DRAW_PM4 128 +/* R600_CLIP */ +#define R600_CLIP__PA_CL_UCP_X_0 0 +#define R600_CLIP__PA_CL_UCP_Y_0 1 +#define R600_CLIP__PA_CL_UCP_Z_0 2 +#define R600_CLIP__PA_CL_UCP_W_0 3 +#define R600_CLIP_SIZE 4 +#define R600_CLIP_PM4 128 /* R600 QUERY BEGIN/END */ -#define R600_QUERY__OFFSET 0 -#define R600_QUERY__BO_ID 3 +#define R600_QUERY__OFFSET 0 +#define R600_QUERY_SIZE 1 +#define R600_QUERY_PM4 128 #endif diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c index 79415632151..9b7c11bdc06 100644 --- a/src/gallium/winsys/r600/drm/r600_state.c +++ b/src/gallium/winsys/r600/drm/r600_state.c @@ -30,41 +30,377 @@ #include "radeon_priv.h" #include "r600d.h" -static const struct radeon_type R600_types[]; -static const struct radeon_type R700_types[]; -#define R600_FLUSH_RESOURCE ((~C_0085F0_TC_ACTION_ENA) | (~C_0085F0_VC_ACTION_ENA)) -#define R600_FLUSH_CB0 (~C_0085F0_CB0_DEST_BASE_ENA) -#define R600_FLUSH_CB1 (~C_0085F0_CB1_DEST_BASE_ENA) -#define R600_FLUSH_CB2 (~C_0085F0_CB2_DEST_BASE_ENA) -#define R600_FLUSH_CB3 (~C_0085F0_CB3_DEST_BASE_ENA) -#define R600_FLUSH_CB4 (~C_0085F0_CB4_DEST_BASE_ENA) -#define R600_FLUSH_CB5 (~C_0085F0_CB5_DEST_BASE_ENA) -#define R600_FLUSH_CB6 (~C_0085F0_CB6_DEST_BASE_ENA) -#define R600_FLUSH_CB7 (~C_0085F0_CB7_DEST_BASE_ENA) -#define R600_FLUSH_DB (~C_0085F0_DB_DEST_BASE_ENA) -#define R600_DIRTY_ALL 0xFFFFFFFF -#define R600_DIRTY_ALL2 (R600_FLUSH_RESOURCE | R600_FLUSH_DB | R600_FLUSH_CB0\ - R600_FLUSH_CB1 | R600_FLUSH_CB2 | R600_FLUSH_CB3\ - R600_FLUSH_CB4 | R600_FLUSH_CB5 | R600_FLUSH_CB6\ - R600_FLUSH_CB7) +static int r600_state_pm4_resource(struct radeon_state *state); +static int r600_state_pm4_cb0(struct radeon_state *state); +static int r600_state_pm4_vgt(struct radeon_state *state); +static int r600_state_pm4_db(struct radeon_state *state); +static int r600_state_pm4_shader(struct radeon_state *state); +static int r600_state_pm4_draw(struct radeon_state *state); +static int r600_state_pm4_config(struct radeon_state *state); +static int r600_state_pm4_generic(struct radeon_state *state); +static int r600_state_pm4_query_begin(struct radeon_state *state); +static int r600_state_pm4_query_end(struct radeon_state *state); +static int r700_state_pm4_config(struct radeon_state *state); +static int r700_state_pm4_cb0(struct radeon_state *state); +static int r700_state_pm4_db(struct radeon_state *state); -static int r600_ctx_bo_flush(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement) +#include "r600_states.h" + +/* + * r600/r700 state functions + */ +static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg) +{ + const struct radeon_register *regs = state->radeon->type[state->type].regs; + unsigned i; + int r; + + if (!offset) { + fprintf(stderr, "%s invalid register for state %d %d\n", + __func__, state->type, id); + return -EINVAL; + } + if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg); + state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + for (i = 0; i < nreg; i++) { + if (regs[id + i].need_reloc) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle; + } + } + return 0; + } + if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg); + state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + for (i = 0; i < nreg; i++) { + if (regs[id + i].need_reloc) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle; + } + } + return 0; + } + if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg); + state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + return 0; + } + if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) { + state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg); + state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2; + for (i = 0; i < nreg; i++) { + state->pm4[state->cpm4++] = state->states[id + i]; + } + return 0; + } + fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset); + return -EINVAL; +} + +static int r600_state_pm4_generic(struct radeon_state *state) +{ + struct radeon *radeon = state->radeon; + unsigned i, offset, nreg, type, coffset, loffset, soffset; + unsigned start; + int r; + + if (!state->nstates) + return 0; + type = state->type; + soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride; + offset = loffset = radeon->type[type].regs[0].offset + soffset; + start = 0; + for (i = 1, nreg = 1; i < state->nstates; i++) { + coffset = radeon->type[type].regs[i].offset + soffset; + if (coffset == (loffset + 4)) { + nreg++; + loffset = coffset; + } else { + r = r600_state_pm4_bytecode(state, offset, start, nreg); + if (r) { + fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg); + return r; + } + offset = loffset = coffset; + nreg = 1; + start = i; + } + } + return r600_state_pm4_bytecode(state, offset, start, nreg); +} + +static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags) +{ + unsigned i, j, add, size; + + state->nreloc = 0; + for (i = 0; i < state->nbo; i++) { + for (j = 0, add = 1; j < state->nreloc; j++) { + if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) { + add = 0; + break; + } + } + if (add) { + state->reloc_bo_id[state->nreloc++] = i; + } + } + for (i = 0; i < state->nreloc; i++) { + size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3); + state->pm4[state->cpm4++] = flags; + state->pm4[state->cpm4++] = size; + state->pm4[state->cpm4++] = 0x00000000; + state->pm4[state->cpm4++] = 0x0000000A; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + state->reloc_pm4_id[i] = state->cpm4; + state->pm4[state->cpm4++] = state->bo[state->reloc_bo_id[i]]->handle; + } +} + +static int r600_state_pm4_cb0(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) | + S_0085F0_CB0_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); + state->pm4[state->cpm4++] = 0x00000002; + return 0; +} + +static int r700_state_pm4_cb0(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) | + S_0085F0_CB0_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + return 0; +} + +static int r600_state_pm4_db(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0); + state->pm4[state->cpm4++] = 0x00000001; + return 0; +} + +static int r700_state_pm4_db(struct radeon_state *state) +{ + int r; + + r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) | + S_0085F0_DB_DEST_BASE_ENA(1)); + r = r600_state_pm4_generic(state); + if (r) + return r; + return 0; +} + +static int r600_state_pm4_config(struct radeon_state *state) +{ + state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0); + state->pm4[state->cpm4++] = 0x00000000; + state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); + state->pm4[state->cpm4++] = 0x00000010; + state->pm4[state->cpm4++] = 0x00028000; + return r600_state_pm4_generic(state); +} + +static int r600_state_pm4_query_begin(struct radeon_state *state) +{ + int r; + + state->cpm4 = 0; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); + state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = 0x0; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + return 0; +} + +static int r600_state_pm4_query_end(struct radeon_state *state) +{ + int r; + + state->cpm4 = 0; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2); + state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = 0x0; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + return 0; +} + +static int r700_state_pm4_config(struct radeon_state *state) +{ + state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1); + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = 0x80000000; + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1); + state->pm4[state->cpm4++] = 0x00000010; + state->pm4[state->cpm4++] = 0x00028000; + return r600_state_pm4_generic(state); +} + +static int r600_state_pm4_shader(struct radeon_state *state) +{ + r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1)); + return r600_state_pm4_generic(state); +} + +static int r600_state_pm4_vgt(struct radeon_state *state) +{ + int r; + + r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1); + if (r) + return r; + r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1); + if (r) + return r; + state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0); + state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE]; + state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0); + state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES]; + return 0; +} + +static int r600_state_pm4_draw(struct radeon_state *state) { - unsigned size; + unsigned i; + int r; - if (7 > ctx->npm4) { - return -EBUSY; + if (state->nbo) { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + } else if (state->nimmd) { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; + for (i = 0; i < state->nimmd; i++) { + state->pm4[state->cpm4++] = state->immd[i]; + } + } else { + state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1); + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES]; + state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR]; } - size = (bo->size + 255) >> 8; - ctx->pm4[ctx->id++] = PKT3(PKT3_SURFACE_SYNC, 3); - ctx->pm4[ctx->id++] = flags; - ctx->pm4[ctx->id++] = size; - ctx->pm4[ctx->id++] = 0x00000000; - ctx->pm4[ctx->id++] = 0x0000000A; - ctx->pm4[ctx->id++] = PKT3(PKT3_NOP, 0); - ctx->pm4[ctx->id++] = 0x00000000; - ctx->npm4 -= 7; - return radeon_ctx_reloc(ctx, bo, ctx->id - 1, placement); + state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0); + state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; + return 0; +} + +static int r600_state_pm4_resource(struct radeon_state *state) +{ + u32 flags, type, nbo, offset, soffset; + int r; + + soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride; + type = G_038018_TYPE(state->states[6]); + switch (type) { + case 2: + flags = S_0085F0_TC_ACTION_ENA(1); + nbo = 2; + break; + case 3: + flags = S_0085F0_VC_ACTION_ENA(1); + nbo = 1; + break; + default: + return 0; + } + if (state->nbo != nbo) { + fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo); + return -EINVAL; + } + r600_state_pm4_with_flush(state, flags); + offset = state->radeon->type[state->type].regs[0].offset + soffset; + state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7); + state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2; + state->pm4[state->cpm4++] = state->states[0]; + state->pm4[state->cpm4++] = state->states[1]; + state->pm4[state->cpm4++] = state->states[2]; + state->pm4[state->cpm4++] = state->states[3]; + state->pm4[state->cpm4++] = state->states[4]; + state->pm4[state->cpm4++] = state->states[5]; + state->pm4[state->cpm4++] = state->states[6]; + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 0); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[0]->handle; + if (type == 2) { + state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0); + r = radeon_state_reloc(state, state->cpm4, 1); + if (r) + return r; + state->pm4[state->cpm4++] = state->bo[1]->handle; + } + return 0; } int r600_init(struct radeon *radeon) @@ -78,6 +414,7 @@ int r600_init(struct radeon *radeon) case CHIP_RV635: case CHIP_RS780: case CHIP_RS880: + radeon->ntype = R600_NTYPE; radeon->nstate = R600_NSTATE; radeon->type = R600_types; break; @@ -85,6 +422,7 @@ int r600_init(struct radeon *radeon) case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: + radeon->ntype = R600_NTYPE; radeon->nstate = R600_NSTATE; radeon->type = R700_types; break; @@ -93,7696 +431,5 @@ int r600_init(struct radeon *radeon) __func__, radeon->device); return -EINVAL; } - radeon->bo_flush = &r600_ctx_bo_flush; return 0; } - -/* CONFIG */ -#define R600_CONFIG_header_cpm4 12 -static const u32 R600_CONFIG_header_pm4[R600_CONFIG_header_cpm4] = { - 0xC0002400, - 0x00000000, - 0xC0012800, - 0x80000000, - 0x80000000, - 0xC0004600, - 0x00000016, - 0xC0016800, - 0x00000010, - 0x00028000, - 0xC0066800, - 0x00000300, -}; -#define R700_CONFIG_header_cpm4 10 -u32 R700_CONFIG_header_pm4[R700_CONFIG_header_cpm4] = { - 0xC0012800, - 0x80000000, - 0x80000000, - 0xC0004600, - 0x00000016, - 0xC0016800, - 0x00000010, - 0x00028000, - 0xC0066800, - 0x00000300, -}; -#define R600_CONFIG_state_cpm4 67 -u32 R600_CONFIG_state_pm4[R600_CONFIG_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016800, - 0x00000363, - 0x00000000, - 0xC0016800, - 0x00000542, - 0x00000000, - 0xC0016800, - 0x000005C5, - 0x00000000, - 0xC0016800, - 0x0000060C, - 0x00000000, - 0xC0016800, - 0x0000060E, - 0x00000000, - 0xC0016900, - 0x000000D4, - 0x00000000, - 0xC0016900, - 0x000001B2, - 0x00000000, - 0xC0016900, - 0x000001E8, - 0x00000000, - 0xC0096900, - 0x0000022A, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC00D6900, - 0x00000284, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000293, - 0x00000000, - 0xC0036900, - 0x000002AC, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x000002C8, - 0x00000000, -}; -#define R600_CB_CNTL_header_cpm4 2 -u32 R600_CB_CNTL_header_pm4[R600_CB_CNTL_header_cpm4] = { - 0xC0046900, - 0x00000048, -}; -#define R600_CB_CNTL_state_cpm4 32 -u32 R600_CB_CNTL_state_pm4[R600_CB_CNTL_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x0000008E, - 0x00000000, - 0x00000000, - 0xC0036900, - 0x00000109, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000202, - 0x00000000, - 0xC0016900, - 0x00000301, - 0x00000000, - 0xC0026900, - 0x00000307, - 0x00000000, - 0x00000000, - 0xC0046900, - 0x0000030C, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000312, - 0x00000000, -}; -#define R600_RASTERIZER_header_cpm4 2 -u32 R600_RASTERIZER_header_pm4[R600_RASTERIZER_header_cpm4] = { - 0xC0016900, - 0x000001B5, -}; -#define R600_RASTERIZER_state_cpm4 35 -u32 R600_RASTERIZER_state_pm4[R600_RASTERIZER_state_cpm4] = { - 0x00000000, - 0xC0026900, - 0x00000204, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x00000207, - 0x00000000, - 0x00000000, - 0xC0046900, - 0x00000280, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000292, - 0x00000000, - 0xC0016900, - 0x00000300, - 0x00000000, - 0xC0046900, - 0x00000303, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0066900, - 0x0000037E, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -/* R600_VIEWPORT */ -#define R600_VIEWPORT_header_cpm4 2 -u32 R600_VIEWPORT_header_pm4[R600_VIEWPORT_header_cpm4] = { - 0xC0026900, - 0x000000B4, -}; -#define R600_VIEWPORT_state_cpm4 23 -u32 R600_VIEWPORT_state_pm4[R600_VIEWPORT_state_cpm4] = { - 0x00000000, - 0x00000000, - 0xC0016900, - 0x0000010F, - 0x00000000, - 0xC0016900, - 0x00000111, - 0x00000000, - 0xC0016900, - 0x00000113, - 0x00000000, - 0xC0016900, - 0x00000110, - 0x00000000, - 0xC0016900, - 0x00000112, - 0x00000000, - 0xC0016900, - 0x00000114, - 0x00000000, - 0xC0016900, - 0x00000206, - 0x00000000, -}; -#define R600_SCISSOR_header_cpm4 2 -u32 R600_SCISSOR_header_pm4[R600_SCISSOR_header_cpm4] = { - 0xC0026900, - 0x0000000C, -}; -#define R600_SCISSOR_state_cpm4 25 -u32 R600_SCISSOR_state_pm4[R600_SCISSOR_state_cpm4] = { - 0x00000000, - 0x00000000, - 0xC00D6900, - 0x00000080, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x00000090, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x00000094, - 0x00000000, - 0x00000000, -}; - -/* R600_BLEND */ -#define R600_BLEND_header_cpm4 2 -u32 R600_BLEND_header_pm4[R600_BLEND_header_cpm4] = { - 0xC0046900, - 0x00000105, -}; -#define R600_BLEND_state_cpm4 17 -u32 R600_BLEND_state_pm4[R600_BLEND_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0086900, - 0x000001E0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000201, - 0x00000000, -}; - -/* R600_DSA */ -#define R600_DSA_header_cpm4 2 -u32 R600_DSA_header_pm4[R600_DSA_header_cpm4] = { - 0xC0026900, - 0x0000000A, -}; -#define R600_DSA_state_cpm4 34 -u32 R600_DSA_state_pm4[R600_DSA_state_cpm4] = { - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000104, - 0x00000000, - 0xC0036900, - 0x0000010C, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x000001B8, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x000001B7, - 0x00000000, - 0xC0016900, - 0x00000200, - 0x00000000, - 0xC0016900, - 0x00000203, - 0x00000000, - 0xC0026900, - 0x00000343, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x0000034B, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000351, - 0x00000000, -}; - -/* R600_UCP */ -#define R600_UCP_header_cpm4 2 -u32 R600_UCP0_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x00000388, -}; -u32 R600_UCP1_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x0000038C, -}; -u32 R600_UCP2_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x00000390, -}; -u32 R600_UCP3_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x00000394, -}; -u32 R600_UCP4_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x00000398, -}; -u32 R600_UCP5_header_pm4[R600_UCP_header_cpm4] = { - 0xC0046900, - 0x0000039C, -}; -#define R600_UCP_state_cpm4 4 -u32 R600_UCP_state_pm4[R600_UCP_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -/* R600_VGT */ -#define R600_VGT_header_cpm4 2 -u32 R600_VGT_header_pm4[R600_VGT_header_cpm4] = { - 0xC0046900, - 0x00000100, -}; -#define R600_VGT_state_cpm4 11 -u32 R600_VGT_state_pm4[R600_VGT_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016800, - 0x00000256, - 0x00000000, - 0xC0002A00, - 0x00000000, - 0xC0002F00, - 0x00000000, -}; - -/* R600_QUERY */ -#define R600_QUERY_header_cpm4 2 -u32 R600_QUERY_header_pm4[R600_QUERY_header_cpm4] = { - 0xC0024600, - 0x00000015, -}; -#define R600_QUERY_state_cpm4 4 -u32 R600_QUERY_state_pm4[R600_QUERY_state_cpm4] = { - 0x00000000, - 0x00000000, - 0xC0001000, - 0x00000000, -}; - -/* R600_DRAW_AUTO */ -#define R600_DRAW_AUTO_header_cpm4 1 -u32 R600_DRAW_AUTO_header_pm4[R600_DRAW_AUTO_header_cpm4] = { - 0xC0012D00, -}; -#define R600_DRAW_AUTO_state_cpm4 4 -u32 R600_DRAW_AUTO_state_pm4[R600_DRAW_AUTO_state_cpm4] = { - 0x00000000, - 0x00000000, - 0xC0004600, - 0x00000016, -}; - -/* R600_DRAW */ -#define R600_DRAW_header_cpm4 1 -u32 R600_DRAW_header_pm4[R600_DRAW_header_cpm4] = { - 0xC0032B00, -}; -#define R600_DRAW_state_cpm4 8 -u32 R600_DRAW_state_pm4[R600_DRAW_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0004600, - 0x00000016, -}; - -/* R600_VS_SHADER */ -#define R600_VS_SHADER_header_cpm4 2 -u32 R600_VS_SHADER_header_pm4[R600_VS_SHADER_header_cpm4] = { - 0xC0206900, - 0x000000E0, -}; -#define R600_VS_SHADER_state_cpm4 69 -u32 R600_VS_SHADER_state_pm4[R600_VS_SHADER_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC00A6900, - 0x00000185, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x000001B1, - 0x00000000, - 0xC0016900, - 0x00000216, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x0000021A, - 0x00000000, - 0xC0016900, - 0x00000225, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000229, - 0x00000000, - 0xC0016900, - 0x00000234, - 0x00000000, - 0xC0016900, - 0x00000237, - 0x00000000, -}; - -/* R600_PS_SHADER */ -#define R600_PS_SHADER_header_cpm4 2 -u32 R600_PS_SHADER_header_pm4[R600_PS_SHADER_header_cpm4] = { - 0xC0206900, - 0x00000191, -}; -#define R600_PS_SHADER_state_cpm4 51 -u32 R600_PS_SHADER_state_pm4[R600_PS_SHADER_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0026900, - 0x000001B3, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x000001B6, - 0x00000000, - 0xC0016900, - 0x00000210, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0026900, - 0x00000214, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000233, - 0x00000000, -}; - -/* R600_DB */ -#define R600_DB_header_cpm4 2 -u32 R600_DB_header_pm4[R600_DB_header_cpm4] = { - 0xC0016900, - 0x00000003, -}; -#define R600_DB_state_cpm4 18 -u32 R600_DB_state_pm4[R600_DB_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0026900, - 0x00000000, - 0x00000000, - 0x00000000, - 0xC0016900, - 0x00000004, - 0x00000000, - 0xC0016900, - 0x00000349, - 0x00000000, - 0xC0016900, - 0x0000034D, - 0x00000000, - 0xC0007300, - 0x00000001, -}; - -/* R600_CB0 */ -#define R600_CB0_header_cpm4 2 -u32 R600_CB0_header_pm4[R600_CB0_header_cpm4] = { - 0xC0016900, - 0x00000010, -}; -#define R600_CB0_state_cpm4 27 -u32 R600_CB0_state_pm4[R600_CB0_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000028, - 0x00000000, - 0xC0016900, - 0x00000018, - 0x00000000, - 0xC0016900, - 0x00000020, - 0x00000000, - 0xC0016900, - 0x00000038, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000030, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000040, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB1 */ -#define R600_CB1_header_cpm4 2 -u32 R600_CB1_header_pm4[R600_CB1_header_cpm4] = { - 0xC0016900, - 0x00000011, -}; -#define R600_CB1_state_cpm4 27 -u32 R600_CB1_state_pm4[R600_CB1_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000029, - 0x00000000, - 0xC0016900, - 0x00000019, - 0x00000000, - 0xC0016900, - 0x00000021, - 0x00000000, - 0xC0016900, - 0x00000039, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000031, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000041, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB2 */ -#define R600_CB2_header_cpm4 2 -u32 R600_CB2_header_pm4[R600_CB2_header_cpm4] = { - 0xC0016900, - 0x00000012, -}; -#define R600_CB2_state_cpm4 27 -u32 R600_CB2_state_pm4[R600_CB2_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002A, - 0x00000000, - 0xC0016900, - 0x0000001A, - 0x00000000, - 0xC0016900, - 0x00000022, - 0x00000000, - 0xC0016900, - 0x0000003A, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000032, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000042, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB3 */ -#define R600_CB3_header_cpm4 2 -u32 R600_CB3_header_pm4[R600_CB3_header_cpm4] = { - 0xC0016900, - 0x00000013, -}; -#define R600_CB3_state_cpm4 27 -u32 R600_CB3_state_pm4[R600_CB3_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002B, - 0x00000000, - 0xC0016900, - 0x0000001B, - 0x00000000, - 0xC0016900, - 0x00000023, - 0x00000000, - 0xC0016900, - 0x0000003B, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000033, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000043, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB4 */ -#define R600_CB4_header_cpm4 2 -u32 R600_CB4_header_pm4[R600_CB4_header_cpm4] = { - 0xC0016900, - 0x00000014, -}; -#define R600_CB4_state_cpm4 27 -u32 R600_CB4_state_pm4[R600_CB4_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002C, - 0x00000000, - 0xC0016900, - 0x0000001C, - 0x00000000, - 0xC0016900, - 0x00000024, - 0x00000000, - 0xC0016900, - 0x0000003C, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000034, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000044, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB5 */ -#define R600_CB5_header_cpm4 2 -u32 R600_CB5_header_pm4[R600_CB5_header_cpm4] = { - 0xC0016900, - 0x00000015, -}; -#define R600_CB5_state_cpm4 27 -u32 R600_CB5_state_pm4[R600_CB5_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002D, - 0x00000000, - 0xC0016900, - 0x0000001D, - 0x00000000, - 0xC0016900, - 0x00000025, - 0x00000000, - 0xC0016900, - 0x0000003D, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000035, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000045, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB6 */ -#define R600_CB6_header_cpm4 2 -u32 R600_CB6_header_pm4[R600_CB6_header_cpm4] = { - 0xC0016900, - 0x00000016, -}; -#define R600_CB6_state_cpm4 27 -u32 R600_CB6_state_pm4[R600_CB6_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002E, - 0x00000000, - 0xC0016900, - 0x0000001E, - 0x00000000, - 0xC0016900, - 0x00000026, - 0x00000000, - 0xC0016900, - 0x0000003E, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000036, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000046, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CB7 */ -#define R600_CB7_header_cpm4 2 -u32 R600_CB7_header_pm4[R600_CB7_header_cpm4] = { - 0xC0016900, - 0x00000017, -}; -#define R600_CB7_state_cpm4 27 -u32 R600_CB7_state_pm4[R600_CB7_state_cpm4] = { - 0x00000000, - 0xC0001000, - 0x00000004, - 0xC0016900, - 0x0000002F, - 0x00000000, - 0xC0016900, - 0x0000001F, - 0x00000000, - 0xC0016900, - 0x00000027, - 0x00000000, - 0xC0016900, - 0x0000003F, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000037, - 0x00000000, - 0xC0001000, - 0x00000000, - 0xC0016900, - 0x00000047, - 0x00000000, - 0xC0007300, - 0x00000002, -}; - -/* R600_CONSTANT */ -#define R600_CONSTANT_header_cpm4 2 -u32 R600_PS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000000, -}; -u32 R600_PS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000004, -}; -u32 R600_PS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000008, -}; -u32 R600_PS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000000C, -}; -u32 R600_PS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000010, -}; -u32 R600_PS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000014, -}; -u32 R600_PS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000018, -}; -u32 R600_PS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000001C, -}; -u32 R600_PS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000020, -}; -u32 R600_PS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000024, -}; -u32 R600_PS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000028, -}; -u32 R600_PS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000002C, -}; -u32 R600_PS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000030, -}; -u32 R600_PS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000034, -}; -u32 R600_PS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000038, -}; -u32 R600_PS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000003C, -}; -u32 R600_PS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000040, -}; -u32 R600_PS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000044, -}; -u32 R600_PS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000048, -}; -u32 R600_PS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000004C, -}; -u32 R600_PS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000050, -}; -u32 R600_PS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000054, -}; -u32 R600_PS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000058, -}; -u32 R600_PS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000005C, -}; -u32 R600_PS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000060, -}; -u32 R600_PS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000064, -}; -u32 R600_PS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000068, -}; -u32 R600_PS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000006C, -}; -u32 R600_PS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000070, -}; -u32 R600_PS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000074, -}; -u32 R600_PS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000078, -}; -u32 R600_PS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000007C, -}; -u32 R600_PS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000080, -}; -u32 R600_PS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000084, -}; -u32 R600_PS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000088, -}; -u32 R600_PS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000008C, -}; -u32 R600_PS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000090, -}; -u32 R600_PS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000094, -}; -u32 R600_PS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000098, -}; -u32 R600_PS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000009C, -}; -u32 R600_PS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000A0, -}; -u32 R600_PS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000A4, -}; -u32 R600_PS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000A8, -}; -u32 R600_PS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000AC, -}; -u32 R600_PS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000B0, -}; -u32 R600_PS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000B4, -}; -u32 R600_PS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000B8, -}; -u32 R600_PS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000BC, -}; -u32 R600_PS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000C0, -}; -u32 R600_PS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000C4, -}; -u32 R600_PS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000C8, -}; -u32 R600_PS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000CC, -}; -u32 R600_PS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000D0, -}; -u32 R600_PS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000D4, -}; -u32 R600_PS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000D8, -}; -u32 R600_PS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000DC, -}; -u32 R600_PS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000E0, -}; -u32 R600_PS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000E4, -}; -u32 R600_PS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000E8, -}; -u32 R600_PS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000EC, -}; -u32 R600_PS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000F0, -}; -u32 R600_PS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000F4, -}; -u32 R600_PS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000F8, -}; -u32 R600_PS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000000FC, -}; -u32 R600_PS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000100, -}; -u32 R600_PS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000104, -}; -u32 R600_PS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000108, -}; -u32 R600_PS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000010C, -}; -u32 R600_PS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000110, -}; -u32 R600_PS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000114, -}; -u32 R600_PS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000118, -}; -u32 R600_PS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000011C, -}; -u32 R600_PS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000120, -}; -u32 R600_PS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000124, -}; -u32 R600_PS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000128, -}; -u32 R600_PS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000012C, -}; -u32 R600_PS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000130, -}; -u32 R600_PS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000134, -}; -u32 R600_PS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000138, -}; -u32 R600_PS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000013C, -}; -u32 R600_PS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000140, -}; -u32 R600_PS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000144, -}; -u32 R600_PS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000148, -}; -u32 R600_PS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000014C, -}; -u32 R600_PS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000150, -}; -u32 R600_PS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000154, -}; -u32 R600_PS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000158, -}; -u32 R600_PS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000015C, -}; -u32 R600_PS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000160, -}; -u32 R600_PS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000164, -}; -u32 R600_PS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000168, -}; -u32 R600_PS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000016C, -}; -u32 R600_PS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000170, -}; -u32 R600_PS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000174, -}; -u32 R600_PS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000178, -}; -u32 R600_PS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000017C, -}; -u32 R600_PS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000180, -}; -u32 R600_PS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000184, -}; -u32 R600_PS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000188, -}; -u32 R600_PS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000018C, -}; -u32 R600_PS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000190, -}; -u32 R600_PS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000194, -}; -u32 R600_PS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000198, -}; -u32 R600_PS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000019C, -}; -u32 R600_PS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001A0, -}; -u32 R600_PS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001A4, -}; -u32 R600_PS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001A8, -}; -u32 R600_PS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001AC, -}; -u32 R600_PS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001B0, -}; -u32 R600_PS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001B4, -}; -u32 R600_PS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001B8, -}; -u32 R600_PS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001BC, -}; -u32 R600_PS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001C0, -}; -u32 R600_PS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001C4, -}; -u32 R600_PS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001C8, -}; -u32 R600_PS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001CC, -}; -u32 R600_PS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001D0, -}; -u32 R600_PS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001D4, -}; -u32 R600_PS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001D8, -}; -u32 R600_PS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001DC, -}; -u32 R600_PS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001E0, -}; -u32 R600_PS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001E4, -}; -u32 R600_PS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001E8, -}; -u32 R600_PS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001EC, -}; -u32 R600_PS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001F0, -}; -u32 R600_PS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001F4, -}; -u32 R600_PS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001F8, -}; -u32 R600_PS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000001FC, -}; -u32 R600_PS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000200, -}; -u32 R600_PS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000204, -}; -u32 R600_PS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000208, -}; -u32 R600_PS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000020C, -}; -u32 R600_PS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000210, -}; -u32 R600_PS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000214, -}; -u32 R600_PS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000218, -}; -u32 R600_PS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000021C, -}; -u32 R600_PS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000220, -}; -u32 R600_PS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000224, -}; -u32 R600_PS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000228, -}; -u32 R600_PS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000022C, -}; -u32 R600_PS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000230, -}; -u32 R600_PS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000234, -}; -u32 R600_PS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000238, -}; -u32 R600_PS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000023C, -}; -u32 R600_PS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000240, -}; -u32 R600_PS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000244, -}; -u32 R600_PS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000248, -}; -u32 R600_PS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000024C, -}; -u32 R600_PS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000250, -}; -u32 R600_PS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000254, -}; -u32 R600_PS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000258, -}; -u32 R600_PS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000025C, -}; -u32 R600_PS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000260, -}; -u32 R600_PS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000264, -}; -u32 R600_PS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000268, -}; -u32 R600_PS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000026C, -}; -u32 R600_PS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000270, -}; -u32 R600_PS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000274, -}; -u32 R600_PS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000278, -}; -u32 R600_PS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000027C, -}; -u32 R600_PS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000280, -}; -u32 R600_PS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000284, -}; -u32 R600_PS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000288, -}; -u32 R600_PS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000028C, -}; -u32 R600_PS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000290, -}; -u32 R600_PS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000294, -}; -u32 R600_PS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000298, -}; -u32 R600_PS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000029C, -}; -u32 R600_PS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002A0, -}; -u32 R600_PS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002A4, -}; -u32 R600_PS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002A8, -}; -u32 R600_PS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002AC, -}; -u32 R600_PS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002B0, -}; -u32 R600_PS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002B4, -}; -u32 R600_PS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002B8, -}; -u32 R600_PS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002BC, -}; -u32 R600_PS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002C0, -}; -u32 R600_PS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002C4, -}; -u32 R600_PS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002C8, -}; -u32 R600_PS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002CC, -}; -u32 R600_PS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002D0, -}; -u32 R600_PS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002D4, -}; -u32 R600_PS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002D8, -}; -u32 R600_PS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002DC, -}; -u32 R600_PS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002E0, -}; -u32 R600_PS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002E4, -}; -u32 R600_PS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002E8, -}; -u32 R600_PS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002EC, -}; -u32 R600_PS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002F0, -}; -u32 R600_PS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002F4, -}; -u32 R600_PS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002F8, -}; -u32 R600_PS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000002FC, -}; -u32 R600_PS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000300, -}; -u32 R600_PS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000304, -}; -u32 R600_PS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000308, -}; -u32 R600_PS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000030C, -}; -u32 R600_PS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000310, -}; -u32 R600_PS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000314, -}; -u32 R600_PS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000318, -}; -u32 R600_PS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000031C, -}; -u32 R600_PS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000320, -}; -u32 R600_PS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000324, -}; -u32 R600_PS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000328, -}; -u32 R600_PS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000032C, -}; -u32 R600_PS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000330, -}; -u32 R600_PS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000334, -}; -u32 R600_PS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000338, -}; -u32 R600_PS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000033C, -}; -u32 R600_PS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000340, -}; -u32 R600_PS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000344, -}; -u32 R600_PS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000348, -}; -u32 R600_PS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000034C, -}; -u32 R600_PS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000350, -}; -u32 R600_PS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000354, -}; -u32 R600_PS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000358, -}; -u32 R600_PS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000035C, -}; -u32 R600_PS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000360, -}; -u32 R600_PS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000364, -}; -u32 R600_PS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000368, -}; -u32 R600_PS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000036C, -}; -u32 R600_PS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000370, -}; -u32 R600_PS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000374, -}; -u32 R600_PS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000378, -}; -u32 R600_PS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000037C, -}; -u32 R600_PS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000380, -}; -u32 R600_PS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000384, -}; -u32 R600_PS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000388, -}; -u32 R600_PS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000038C, -}; -u32 R600_PS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000390, -}; -u32 R600_PS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000394, -}; -u32 R600_PS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000398, -}; -u32 R600_PS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000039C, -}; -u32 R600_PS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003A0, -}; -u32 R600_PS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003A4, -}; -u32 R600_PS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003A8, -}; -u32 R600_PS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003AC, -}; -u32 R600_PS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003B0, -}; -u32 R600_PS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003B4, -}; -u32 R600_PS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003B8, -}; -u32 R600_PS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003BC, -}; -u32 R600_PS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003C0, -}; -u32 R600_PS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003C4, -}; -u32 R600_PS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003C8, -}; -u32 R600_PS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003CC, -}; -u32 R600_PS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003D0, -}; -u32 R600_PS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003D4, -}; -u32 R600_PS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003D8, -}; -u32 R600_PS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003DC, -}; -u32 R600_PS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003E0, -}; -u32 R600_PS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003E4, -}; -u32 R600_PS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003E8, -}; -u32 R600_PS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003EC, -}; -u32 R600_PS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003F0, -}; -u32 R600_PS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003F4, -}; -u32 R600_PS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003F8, -}; -u32 R600_PS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000003FC, -}; -u32 R600_VS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000400, -}; -u32 R600_VS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000404, -}; -u32 R600_VS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000408, -}; -u32 R600_VS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000040C, -}; -u32 R600_VS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000410, -}; -u32 R600_VS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000414, -}; -u32 R600_VS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000418, -}; -u32 R600_VS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000041C, -}; -u32 R600_VS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000420, -}; -u32 R600_VS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000424, -}; -u32 R600_VS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000428, -}; -u32 R600_VS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000042C, -}; -u32 R600_VS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000430, -}; -u32 R600_VS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000434, -}; -u32 R600_VS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000438, -}; -u32 R600_VS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000043C, -}; -u32 R600_VS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000440, -}; -u32 R600_VS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000444, -}; -u32 R600_VS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000448, -}; -u32 R600_VS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000044C, -}; -u32 R600_VS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000450, -}; -u32 R600_VS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000454, -}; -u32 R600_VS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000458, -}; -u32 R600_VS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000045C, -}; -u32 R600_VS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000460, -}; -u32 R600_VS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000464, -}; -u32 R600_VS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000468, -}; -u32 R600_VS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000046C, -}; -u32 R600_VS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000470, -}; -u32 R600_VS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000474, -}; -u32 R600_VS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000478, -}; -u32 R600_VS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000047C, -}; -u32 R600_VS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000480, -}; -u32 R600_VS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000484, -}; -u32 R600_VS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000488, -}; -u32 R600_VS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000048C, -}; -u32 R600_VS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000490, -}; -u32 R600_VS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000494, -}; -u32 R600_VS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000498, -}; -u32 R600_VS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000049C, -}; -u32 R600_VS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004A0, -}; -u32 R600_VS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004A4, -}; -u32 R600_VS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004A8, -}; -u32 R600_VS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004AC, -}; -u32 R600_VS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004B0, -}; -u32 R600_VS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004B4, -}; -u32 R600_VS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004B8, -}; -u32 R600_VS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004BC, -}; -u32 R600_VS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004C0, -}; -u32 R600_VS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004C4, -}; -u32 R600_VS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004C8, -}; -u32 R600_VS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004CC, -}; -u32 R600_VS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004D0, -}; -u32 R600_VS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004D4, -}; -u32 R600_VS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004D8, -}; -u32 R600_VS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004DC, -}; -u32 R600_VS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004E0, -}; -u32 R600_VS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004E4, -}; -u32 R600_VS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004E8, -}; -u32 R600_VS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004EC, -}; -u32 R600_VS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004F0, -}; -u32 R600_VS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004F4, -}; -u32 R600_VS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004F8, -}; -u32 R600_VS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000004FC, -}; -u32 R600_VS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000500, -}; -u32 R600_VS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000504, -}; -u32 R600_VS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000508, -}; -u32 R600_VS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000050C, -}; -u32 R600_VS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000510, -}; -u32 R600_VS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000514, -}; -u32 R600_VS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000518, -}; -u32 R600_VS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000051C, -}; -u32 R600_VS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000520, -}; -u32 R600_VS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000524, -}; -u32 R600_VS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000528, -}; -u32 R600_VS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000052C, -}; -u32 R600_VS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000530, -}; -u32 R600_VS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000534, -}; -u32 R600_VS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000538, -}; -u32 R600_VS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000053C, -}; -u32 R600_VS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000540, -}; -u32 R600_VS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000544, -}; -u32 R600_VS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000548, -}; -u32 R600_VS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000054C, -}; -u32 R600_VS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000550, -}; -u32 R600_VS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000554, -}; -u32 R600_VS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000558, -}; -u32 R600_VS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000055C, -}; -u32 R600_VS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000560, -}; -u32 R600_VS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000564, -}; -u32 R600_VS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000568, -}; -u32 R600_VS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000056C, -}; -u32 R600_VS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000570, -}; -u32 R600_VS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000574, -}; -u32 R600_VS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000578, -}; -u32 R600_VS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000057C, -}; -u32 R600_VS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000580, -}; -u32 R600_VS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000584, -}; -u32 R600_VS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000588, -}; -u32 R600_VS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000058C, -}; -u32 R600_VS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000590, -}; -u32 R600_VS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000594, -}; -u32 R600_VS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000598, -}; -u32 R600_VS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000059C, -}; -u32 R600_VS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005A0, -}; -u32 R600_VS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005A4, -}; -u32 R600_VS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005A8, -}; -u32 R600_VS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005AC, -}; -u32 R600_VS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005B0, -}; -u32 R600_VS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005B4, -}; -u32 R600_VS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005B8, -}; -u32 R600_VS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005BC, -}; -u32 R600_VS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005C0, -}; -u32 R600_VS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005C4, -}; -u32 R600_VS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005C8, -}; -u32 R600_VS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005CC, -}; -u32 R600_VS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005D0, -}; -u32 R600_VS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005D4, -}; -u32 R600_VS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005D8, -}; -u32 R600_VS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005DC, -}; -u32 R600_VS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005E0, -}; -u32 R600_VS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005E4, -}; -u32 R600_VS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005E8, -}; -u32 R600_VS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005EC, -}; -u32 R600_VS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005F0, -}; -u32 R600_VS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005F4, -}; -u32 R600_VS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005F8, -}; -u32 R600_VS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000005FC, -}; -u32 R600_VS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000600, -}; -u32 R600_VS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000604, -}; -u32 R600_VS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000608, -}; -u32 R600_VS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000060C, -}; -u32 R600_VS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000610, -}; -u32 R600_VS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000614, -}; -u32 R600_VS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000618, -}; -u32 R600_VS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000061C, -}; -u32 R600_VS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000620, -}; -u32 R600_VS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000624, -}; -u32 R600_VS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000628, -}; -u32 R600_VS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000062C, -}; -u32 R600_VS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000630, -}; -u32 R600_VS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000634, -}; -u32 R600_VS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000638, -}; -u32 R600_VS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000063C, -}; -u32 R600_VS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000640, -}; -u32 R600_VS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000644, -}; -u32 R600_VS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000648, -}; -u32 R600_VS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000064C, -}; -u32 R600_VS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000650, -}; -u32 R600_VS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000654, -}; -u32 R600_VS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000658, -}; -u32 R600_VS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000065C, -}; -u32 R600_VS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000660, -}; -u32 R600_VS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000664, -}; -u32 R600_VS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000668, -}; -u32 R600_VS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000066C, -}; -u32 R600_VS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000670, -}; -u32 R600_VS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000674, -}; -u32 R600_VS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000678, -}; -u32 R600_VS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000067C, -}; -u32 R600_VS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000680, -}; -u32 R600_VS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000684, -}; -u32 R600_VS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000688, -}; -u32 R600_VS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000068C, -}; -u32 R600_VS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000690, -}; -u32 R600_VS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000694, -}; -u32 R600_VS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000698, -}; -u32 R600_VS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000069C, -}; -u32 R600_VS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006A0, -}; -u32 R600_VS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006A4, -}; -u32 R600_VS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006A8, -}; -u32 R600_VS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006AC, -}; -u32 R600_VS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006B0, -}; -u32 R600_VS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006B4, -}; -u32 R600_VS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006B8, -}; -u32 R600_VS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006BC, -}; -u32 R600_VS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006C0, -}; -u32 R600_VS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006C4, -}; -u32 R600_VS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006C8, -}; -u32 R600_VS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006CC, -}; -u32 R600_VS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006D0, -}; -u32 R600_VS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006D4, -}; -u32 R600_VS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006D8, -}; -u32 R600_VS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006DC, -}; -u32 R600_VS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006E0, -}; -u32 R600_VS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006E4, -}; -u32 R600_VS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006E8, -}; -u32 R600_VS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006EC, -}; -u32 R600_VS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006F0, -}; -u32 R600_VS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006F4, -}; -u32 R600_VS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006F8, -}; -u32 R600_VS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000006FC, -}; -u32 R600_VS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000700, -}; -u32 R600_VS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000704, -}; -u32 R600_VS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000708, -}; -u32 R600_VS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000070C, -}; -u32 R600_VS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000710, -}; -u32 R600_VS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000714, -}; -u32 R600_VS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000718, -}; -u32 R600_VS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000071C, -}; -u32 R600_VS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000720, -}; -u32 R600_VS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000724, -}; -u32 R600_VS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000728, -}; -u32 R600_VS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000072C, -}; -u32 R600_VS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000730, -}; -u32 R600_VS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000734, -}; -u32 R600_VS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000738, -}; -u32 R600_VS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000073C, -}; -u32 R600_VS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000740, -}; -u32 R600_VS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000744, -}; -u32 R600_VS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000748, -}; -u32 R600_VS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000074C, -}; -u32 R600_VS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000750, -}; -u32 R600_VS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000754, -}; -u32 R600_VS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000758, -}; -u32 R600_VS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000075C, -}; -u32 R600_VS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000760, -}; -u32 R600_VS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000764, -}; -u32 R600_VS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000768, -}; -u32 R600_VS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000076C, -}; -u32 R600_VS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000770, -}; -u32 R600_VS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000774, -}; -u32 R600_VS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000778, -}; -u32 R600_VS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000077C, -}; -u32 R600_VS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000780, -}; -u32 R600_VS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000784, -}; -u32 R600_VS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000788, -}; -u32 R600_VS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000078C, -}; -u32 R600_VS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000790, -}; -u32 R600_VS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000794, -}; -u32 R600_VS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x00000798, -}; -u32 R600_VS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x0000079C, -}; -u32 R600_VS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007A0, -}; -u32 R600_VS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007A4, -}; -u32 R600_VS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007A8, -}; -u32 R600_VS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007AC, -}; -u32 R600_VS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007B0, -}; -u32 R600_VS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007B4, -}; -u32 R600_VS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007B8, -}; -u32 R600_VS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007BC, -}; -u32 R600_VS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007C0, -}; -u32 R600_VS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007C4, -}; -u32 R600_VS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007C8, -}; -u32 R600_VS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007CC, -}; -u32 R600_VS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007D0, -}; -u32 R600_VS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007D4, -}; -u32 R600_VS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007D8, -}; -u32 R600_VS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007DC, -}; -u32 R600_VS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007E0, -}; -u32 R600_VS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007E4, -}; -u32 R600_VS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007E8, -}; -u32 R600_VS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007EC, -}; -u32 R600_VS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007F0, -}; -u32 R600_VS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007F4, -}; -u32 R600_VS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007F8, -}; -u32 R600_VS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = { - 0xC0046A00, - 0x000007FC, -}; -#define R600_CONSTANT_state_cpm4 4 -u32 R600_CONSTANT_state_pm4[R600_CONSTANT_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - - -/* R600_RESOURCE */ -#define R600_RESOURCE_header_cpm4 2 -u32 R600_PS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000000, -}; -u32 R600_PS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000007, -}; -u32 R600_PS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000000E, -}; -u32 R600_PS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000015, -}; -u32 R600_PS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000001C, -}; -u32 R600_PS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000023, -}; -u32 R600_PS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000002A, -}; -u32 R600_PS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000031, -}; -u32 R600_PS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000038, -}; -u32 R600_PS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000003F, -}; -u32 R600_PS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000046, -}; -u32 R600_PS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000004D, -}; -u32 R600_PS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000054, -}; -u32 R600_PS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000005B, -}; -u32 R600_PS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000062, -}; -u32 R600_PS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000069, -}; -u32 R600_PS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000070, -}; -u32 R600_PS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000077, -}; -u32 R600_PS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000007E, -}; -u32 R600_PS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000085, -}; -u32 R600_PS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000008C, -}; -u32 R600_PS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000093, -}; -u32 R600_PS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000009A, -}; -u32 R600_PS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000A1, -}; -u32 R600_PS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000A8, -}; -u32 R600_PS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000AF, -}; -u32 R600_PS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000B6, -}; -u32 R600_PS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000BD, -}; -u32 R600_PS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000C4, -}; -u32 R600_PS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000CB, -}; -u32 R600_PS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000D2, -}; -u32 R600_PS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000D9, -}; -u32 R600_PS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000E0, -}; -u32 R600_PS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000E7, -}; -u32 R600_PS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000EE, -}; -u32 R600_PS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000F5, -}; -u32 R600_PS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000000FC, -}; -u32 R600_PS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000103, -}; -u32 R600_PS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000010A, -}; -u32 R600_PS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000111, -}; -u32 R600_PS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000118, -}; -u32 R600_PS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000011F, -}; -u32 R600_PS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000126, -}; -u32 R600_PS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000012D, -}; -u32 R600_PS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000134, -}; -u32 R600_PS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000013B, -}; -u32 R600_PS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000142, -}; -u32 R600_PS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000149, -}; -u32 R600_PS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000150, -}; -u32 R600_PS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000157, -}; -u32 R600_PS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000015E, -}; -u32 R600_PS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000165, -}; -u32 R600_PS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000016C, -}; -u32 R600_PS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000173, -}; -u32 R600_PS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000017A, -}; -u32 R600_PS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000181, -}; -u32 R600_PS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000188, -}; -u32 R600_PS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000018F, -}; -u32 R600_PS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000196, -}; -u32 R600_PS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000019D, -}; -u32 R600_PS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001A4, -}; -u32 R600_PS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001AB, -}; -u32 R600_PS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001B2, -}; -u32 R600_PS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001B9, -}; -u32 R600_PS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001C0, -}; -u32 R600_PS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001C7, -}; -u32 R600_PS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001CE, -}; -u32 R600_PS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001D5, -}; -u32 R600_PS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001DC, -}; -u32 R600_PS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001E3, -}; -u32 R600_PS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001EA, -}; -u32 R600_PS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001F1, -}; -u32 R600_PS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001F8, -}; -u32 R600_PS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000001FF, -}; -u32 R600_PS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000206, -}; -u32 R600_PS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000020D, -}; -u32 R600_PS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000214, -}; -u32 R600_PS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000021B, -}; -u32 R600_PS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000222, -}; -u32 R600_PS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000229, -}; -u32 R600_PS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000230, -}; -u32 R600_PS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000237, -}; -u32 R600_PS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000023E, -}; -u32 R600_PS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000245, -}; -u32 R600_PS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000024C, -}; -u32 R600_PS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000253, -}; -u32 R600_PS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000025A, -}; -u32 R600_PS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000261, -}; -u32 R600_PS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000268, -}; -u32 R600_PS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000026F, -}; -u32 R600_PS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000276, -}; -u32 R600_PS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000027D, -}; -u32 R600_PS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000284, -}; -u32 R600_PS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000028B, -}; -u32 R600_PS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000292, -}; -u32 R600_PS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000299, -}; -u32 R600_PS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002A0, -}; -u32 R600_PS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002A7, -}; -u32 R600_PS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002AE, -}; -u32 R600_PS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002B5, -}; -u32 R600_PS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002BC, -}; -u32 R600_PS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002C3, -}; -u32 R600_PS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002CA, -}; -u32 R600_PS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002D1, -}; -u32 R600_PS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002D8, -}; -u32 R600_PS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002DF, -}; -u32 R600_PS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002E6, -}; -u32 R600_PS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002ED, -}; -u32 R600_PS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002F4, -}; -u32 R600_PS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000002FB, -}; -u32 R600_PS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000302, -}; -u32 R600_PS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000309, -}; -u32 R600_PS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000310, -}; -u32 R600_PS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000317, -}; -u32 R600_PS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000031E, -}; -u32 R600_PS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000325, -}; -u32 R600_PS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000032C, -}; -u32 R600_PS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000333, -}; -u32 R600_PS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000033A, -}; -u32 R600_PS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000341, -}; -u32 R600_PS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000348, -}; -u32 R600_PS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000034F, -}; -u32 R600_PS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000356, -}; -u32 R600_PS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000035D, -}; -u32 R600_PS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000364, -}; -u32 R600_PS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000036B, -}; -u32 R600_PS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000372, -}; -u32 R600_PS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000379, -}; -u32 R600_PS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000380, -}; -u32 R600_PS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000387, -}; -u32 R600_PS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000038E, -}; -u32 R600_PS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000395, -}; -u32 R600_PS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000039C, -}; -u32 R600_PS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003A3, -}; -u32 R600_PS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003AA, -}; -u32 R600_PS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003B1, -}; -u32 R600_PS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003B8, -}; -u32 R600_PS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003BF, -}; -u32 R600_PS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003C6, -}; -u32 R600_PS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003CD, -}; -u32 R600_PS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003D4, -}; -u32 R600_PS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003DB, -}; -u32 R600_PS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003E2, -}; -u32 R600_PS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003E9, -}; -u32 R600_PS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003F0, -}; -u32 R600_PS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003F7, -}; -u32 R600_PS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000003FE, -}; -u32 R600_PS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000405, -}; -u32 R600_PS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000040C, -}; -u32 R600_PS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000413, -}; -u32 R600_PS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000041A, -}; -u32 R600_PS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000421, -}; -u32 R600_PS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000428, -}; -u32 R600_PS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000042F, -}; -u32 R600_PS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000436, -}; -u32 R600_PS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000043D, -}; -u32 R600_PS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000444, -}; -u32 R600_PS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000044B, -}; -u32 R600_PS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000452, -}; -u32 R600_PS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000459, -}; -u32 R600_VS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000460, -}; -u32 R600_VS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000467, -}; -u32 R600_VS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000046E, -}; -u32 R600_VS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000475, -}; -u32 R600_VS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000047C, -}; -u32 R600_VS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000483, -}; -u32 R600_VS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000048A, -}; -u32 R600_VS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000491, -}; -u32 R600_VS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000498, -}; -u32 R600_VS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000049F, -}; -u32 R600_VS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004A6, -}; -u32 R600_VS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004AD, -}; -u32 R600_VS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004B4, -}; -u32 R600_VS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004BB, -}; -u32 R600_VS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004C2, -}; -u32 R600_VS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004C9, -}; -u32 R600_VS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004D0, -}; -u32 R600_VS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004D7, -}; -u32 R600_VS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004DE, -}; -u32 R600_VS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004E5, -}; -u32 R600_VS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004EC, -}; -u32 R600_VS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004F3, -}; -u32 R600_VS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000004FA, -}; -u32 R600_VS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000501, -}; -u32 R600_VS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000508, -}; -u32 R600_VS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000050F, -}; -u32 R600_VS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000516, -}; -u32 R600_VS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000051D, -}; -u32 R600_VS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000524, -}; -u32 R600_VS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000052B, -}; -u32 R600_VS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000532, -}; -u32 R600_VS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000539, -}; -u32 R600_VS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000540, -}; -u32 R600_VS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000547, -}; -u32 R600_VS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000054E, -}; -u32 R600_VS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000555, -}; -u32 R600_VS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000055C, -}; -u32 R600_VS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000563, -}; -u32 R600_VS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000056A, -}; -u32 R600_VS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000571, -}; -u32 R600_VS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000578, -}; -u32 R600_VS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000057F, -}; -u32 R600_VS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000586, -}; -u32 R600_VS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000058D, -}; -u32 R600_VS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000594, -}; -u32 R600_VS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000059B, -}; -u32 R600_VS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005A2, -}; -u32 R600_VS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005A9, -}; -u32 R600_VS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005B0, -}; -u32 R600_VS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005B7, -}; -u32 R600_VS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005BE, -}; -u32 R600_VS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005C5, -}; -u32 R600_VS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005CC, -}; -u32 R600_VS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005D3, -}; -u32 R600_VS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005DA, -}; -u32 R600_VS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005E1, -}; -u32 R600_VS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005E8, -}; -u32 R600_VS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005EF, -}; -u32 R600_VS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005F6, -}; -u32 R600_VS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000005FD, -}; -u32 R600_VS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000604, -}; -u32 R600_VS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000060B, -}; -u32 R600_VS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000612, -}; -u32 R600_VS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000619, -}; -u32 R600_VS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000620, -}; -u32 R600_VS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000627, -}; -u32 R600_VS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000062E, -}; -u32 R600_VS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000635, -}; -u32 R600_VS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000063C, -}; -u32 R600_VS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000643, -}; -u32 R600_VS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000064A, -}; -u32 R600_VS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000651, -}; -u32 R600_VS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000658, -}; -u32 R600_VS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000065F, -}; -u32 R600_VS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000666, -}; -u32 R600_VS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000066D, -}; -u32 R600_VS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000674, -}; -u32 R600_VS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000067B, -}; -u32 R600_VS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000682, -}; -u32 R600_VS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000689, -}; -u32 R600_VS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000690, -}; -u32 R600_VS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000697, -}; -u32 R600_VS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000069E, -}; -u32 R600_VS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006A5, -}; -u32 R600_VS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006AC, -}; -u32 R600_VS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006B3, -}; -u32 R600_VS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006BA, -}; -u32 R600_VS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006C1, -}; -u32 R600_VS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006C8, -}; -u32 R600_VS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006CF, -}; -u32 R600_VS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006D6, -}; -u32 R600_VS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006DD, -}; -u32 R600_VS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006E4, -}; -u32 R600_VS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006EB, -}; -u32 R600_VS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006F2, -}; -u32 R600_VS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000006F9, -}; -u32 R600_VS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000700, -}; -u32 R600_VS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000707, -}; -u32 R600_VS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000070E, -}; -u32 R600_VS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000715, -}; -u32 R600_VS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000071C, -}; -u32 R600_VS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000723, -}; -u32 R600_VS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000072A, -}; -u32 R600_VS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000731, -}; -u32 R600_VS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000738, -}; -u32 R600_VS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000073F, -}; -u32 R600_VS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000746, -}; -u32 R600_VS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000074D, -}; -u32 R600_VS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000754, -}; -u32 R600_VS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000075B, -}; -u32 R600_VS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000762, -}; -u32 R600_VS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000769, -}; -u32 R600_VS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000770, -}; -u32 R600_VS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000777, -}; -u32 R600_VS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000077E, -}; -u32 R600_VS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000785, -}; -u32 R600_VS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000078C, -}; -u32 R600_VS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000793, -}; -u32 R600_VS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000079A, -}; -u32 R600_VS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007A1, -}; -u32 R600_VS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007A8, -}; -u32 R600_VS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007AF, -}; -u32 R600_VS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007B6, -}; -u32 R600_VS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007BD, -}; -u32 R600_VS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007C4, -}; -u32 R600_VS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007CB, -}; -u32 R600_VS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007D2, -}; -u32 R600_VS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007D9, -}; -u32 R600_VS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007E0, -}; -u32 R600_VS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007E7, -}; -u32 R600_VS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007EE, -}; -u32 R600_VS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007F5, -}; -u32 R600_VS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000007FC, -}; -u32 R600_VS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000803, -}; -u32 R600_VS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000080A, -}; -u32 R600_VS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000811, -}; -u32 R600_VS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000818, -}; -u32 R600_VS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000081F, -}; -u32 R600_VS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000826, -}; -u32 R600_VS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000082D, -}; -u32 R600_VS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000834, -}; -u32 R600_VS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000083B, -}; -u32 R600_VS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000842, -}; -u32 R600_VS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000849, -}; -u32 R600_VS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000850, -}; -u32 R600_VS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000857, -}; -u32 R600_VS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000085E, -}; -u32 R600_VS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000865, -}; -u32 R600_VS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000086C, -}; -u32 R600_VS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000873, -}; -u32 R600_VS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000087A, -}; -u32 R600_VS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000881, -}; -u32 R600_VS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000888, -}; -u32 R600_VS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000088F, -}; -u32 R600_VS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000896, -}; -u32 R600_VS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000089D, -}; -u32 R600_VS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008A4, -}; -u32 R600_VS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008AB, -}; -u32 R600_VS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008B2, -}; -u32 R600_VS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008B9, -}; -u32 R600_FS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008C0, -}; -u32 R600_FS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008C7, -}; -u32 R600_FS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008CE, -}; -u32 R600_FS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008D5, -}; -u32 R600_FS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008DC, -}; -u32 R600_FS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008E3, -}; -u32 R600_FS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008EA, -}; -u32 R600_FS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008F1, -}; -u32 R600_FS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008F8, -}; -u32 R600_FS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000008FF, -}; -u32 R600_FS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000906, -}; -u32 R600_FS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000090D, -}; -u32 R600_FS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000914, -}; -u32 R600_FS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000091B, -}; -u32 R600_FS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000922, -}; -u32 R600_FS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000929, -}; -u32 R600_GS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000930, -}; -u32 R600_GS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000937, -}; -u32 R600_GS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000093E, -}; -u32 R600_GS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000945, -}; -u32 R600_GS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000094C, -}; -u32 R600_GS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000953, -}; -u32 R600_GS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000095A, -}; -u32 R600_GS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000961, -}; -u32 R600_GS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000968, -}; -u32 R600_GS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000096F, -}; -u32 R600_GS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000976, -}; -u32 R600_GS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000097D, -}; -u32 R600_GS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000984, -}; -u32 R600_GS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x0000098B, -}; -u32 R600_GS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000992, -}; -u32 R600_GS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000999, -}; -u32 R600_GS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009A0, -}; -u32 R600_GS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009A7, -}; -u32 R600_GS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009AE, -}; -u32 R600_GS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009B5, -}; -u32 R600_GS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009BC, -}; -u32 R600_GS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009C3, -}; -u32 R600_GS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009CA, -}; -u32 R600_GS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009D1, -}; -u32 R600_GS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009D8, -}; -u32 R600_GS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009DF, -}; -u32 R600_GS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009E6, -}; -u32 R600_GS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009ED, -}; -u32 R600_GS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009F4, -}; -u32 R600_GS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x000009FB, -}; -u32 R600_GS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A02, -}; -u32 R600_GS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A09, -}; -u32 R600_GS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A10, -}; -u32 R600_GS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A17, -}; -u32 R600_GS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A1E, -}; -u32 R600_GS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A25, -}; -u32 R600_GS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A2C, -}; -u32 R600_GS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A33, -}; -u32 R600_GS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A3A, -}; -u32 R600_GS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A41, -}; -u32 R600_GS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A48, -}; -u32 R600_GS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A4F, -}; -u32 R600_GS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A56, -}; -u32 R600_GS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A5D, -}; -u32 R600_GS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A64, -}; -u32 R600_GS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A6B, -}; -u32 R600_GS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A72, -}; -u32 R600_GS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A79, -}; -u32 R600_GS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A80, -}; -u32 R600_GS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A87, -}; -u32 R600_GS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A8E, -}; -u32 R600_GS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A95, -}; -u32 R600_GS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000A9C, -}; -u32 R600_GS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AA3, -}; -u32 R600_GS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AAA, -}; -u32 R600_GS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AB1, -}; -u32 R600_GS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AB8, -}; -u32 R600_GS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000ABF, -}; -u32 R600_GS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AC6, -}; -u32 R600_GS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000ACD, -}; -u32 R600_GS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AD4, -}; -u32 R600_GS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000ADB, -}; -u32 R600_GS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AE2, -}; -u32 R600_GS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AE9, -}; -u32 R600_GS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AF0, -}; -u32 R600_GS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AF7, -}; -u32 R600_GS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000AFE, -}; -u32 R600_GS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B05, -}; -u32 R600_GS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B0C, -}; -u32 R600_GS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B13, -}; -u32 R600_GS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B1A, -}; -u32 R600_GS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B21, -}; -u32 R600_GS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B28, -}; -u32 R600_GS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B2F, -}; -u32 R600_GS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B36, -}; -u32 R600_GS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B3D, -}; -u32 R600_GS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B44, -}; -u32 R600_GS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B4B, -}; -u32 R600_GS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B52, -}; -u32 R600_GS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B59, -}; -u32 R600_GS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B60, -}; -u32 R600_GS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B67, -}; -u32 R600_GS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B6E, -}; -u32 R600_GS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B75, -}; -u32 R600_GS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B7C, -}; -u32 R600_GS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B83, -}; -u32 R600_GS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B8A, -}; -u32 R600_GS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B91, -}; -u32 R600_GS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B98, -}; -u32 R600_GS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000B9F, -}; -u32 R600_GS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BA6, -}; -u32 R600_GS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BAD, -}; -u32 R600_GS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BB4, -}; -u32 R600_GS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BBB, -}; -u32 R600_GS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BC2, -}; -u32 R600_GS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BC9, -}; -u32 R600_GS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BD0, -}; -u32 R600_GS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BD7, -}; -u32 R600_GS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BDE, -}; -u32 R600_GS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BE5, -}; -u32 R600_GS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BEC, -}; -u32 R600_GS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BF3, -}; -u32 R600_GS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000BFA, -}; -u32 R600_GS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C01, -}; -u32 R600_GS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C08, -}; -u32 R600_GS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C0F, -}; -u32 R600_GS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C16, -}; -u32 R600_GS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C1D, -}; -u32 R600_GS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C24, -}; -u32 R600_GS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C2B, -}; -u32 R600_GS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C32, -}; -u32 R600_GS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C39, -}; -u32 R600_GS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C40, -}; -u32 R600_GS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C47, -}; -u32 R600_GS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C4E, -}; -u32 R600_GS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C55, -}; -u32 R600_GS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C5C, -}; -u32 R600_GS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C63, -}; -u32 R600_GS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C6A, -}; -u32 R600_GS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C71, -}; -u32 R600_GS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C78, -}; -u32 R600_GS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C7F, -}; -u32 R600_GS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C86, -}; -u32 R600_GS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C8D, -}; -u32 R600_GS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C94, -}; -u32 R600_GS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000C9B, -}; -u32 R600_GS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CA2, -}; -u32 R600_GS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CA9, -}; -u32 R600_GS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CB0, -}; -u32 R600_GS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CB7, -}; -u32 R600_GS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CBE, -}; -u32 R600_GS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CC5, -}; -u32 R600_GS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CCC, -}; -u32 R600_GS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CD3, -}; -u32 R600_GS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CDA, -}; -u32 R600_GS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CE1, -}; -u32 R600_GS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CE8, -}; -u32 R600_GS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CEF, -}; -u32 R600_GS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CF6, -}; -u32 R600_GS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000CFD, -}; -u32 R600_GS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D04, -}; -u32 R600_GS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D0B, -}; -u32 R600_GS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D12, -}; -u32 R600_GS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D19, -}; -u32 R600_GS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D20, -}; -u32 R600_GS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D27, -}; -u32 R600_GS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D2E, -}; -u32 R600_GS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D35, -}; -u32 R600_GS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D3C, -}; -u32 R600_GS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D43, -}; -u32 R600_GS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D4A, -}; -u32 R600_GS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D51, -}; -u32 R600_GS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D58, -}; -u32 R600_GS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D5F, -}; -u32 R600_GS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D66, -}; -u32 R600_GS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D6D, -}; -u32 R600_GS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D74, -}; -u32 R600_GS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D7B, -}; -u32 R600_GS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D82, -}; -u32 R600_GS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = { - 0xC0076D00, - 0x00000D89, -}; -#define R600_RESOURCE_state_cpm4 11 -u32 R600_RESOURCE_state_pm4[R600_RESOURCE_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x80000000, - 0xC0001000, - 0x00000000, - 0xC0001000, - 0x00000000, -}; - -/* R600_SAMPLER */ -#define R600_SAMPLER_header_cpm4 2 -u32 R600_PS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000000, -}; -u32 R600_PS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000003, -}; -u32 R600_PS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000006, -}; -u32 R600_PS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000009, -}; -u32 R600_PS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000000C, -}; -u32 R600_PS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000000F, -}; -u32 R600_PS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000012, -}; -u32 R600_PS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000015, -}; -u32 R600_PS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000018, -}; -u32 R600_PS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000001B, -}; -u32 R600_PS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000001E, -}; -u32 R600_PS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000021, -}; -u32 R600_PS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000024, -}; -u32 R600_PS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000027, -}; -u32 R600_PS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000002A, -}; -u32 R600_PS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000002D, -}; -u32 R600_PS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000030, -}; -u32 R600_PS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000033, -}; -u32 R600_VS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000036, -}; -u32 R600_VS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000039, -}; -u32 R600_VS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000003C, -}; -u32 R600_VS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000003F, -}; -u32 R600_VS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000042, -}; -u32 R600_VS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000045, -}; -u32 R600_VS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000048, -}; -u32 R600_VS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000004B, -}; -u32 R600_VS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000004E, -}; -u32 R600_VS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000051, -}; -u32 R600_VS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000054, -}; -u32 R600_VS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000057, -}; -u32 R600_VS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000005A, -}; -u32 R600_VS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000005D, -}; -u32 R600_VS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000060, -}; -u32 R600_VS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000063, -}; -u32 R600_VS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000066, -}; -u32 R600_VS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000069, -}; -u32 R600_GS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000006C, -}; -u32 R600_GS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000006F, -}; -u32 R600_GS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000072, -}; -u32 R600_GS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000075, -}; -u32 R600_GS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000078, -}; -u32 R600_GS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000007B, -}; -u32 R600_GS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000007E, -}; -u32 R600_GS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000081, -}; -u32 R600_GS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000084, -}; -u32 R600_GS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000087, -}; -u32 R600_GS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000008A, -}; -u32 R600_GS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000008D, -}; -u32 R600_GS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000090, -}; -u32 R600_GS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000093, -}; -u32 R600_GS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000096, -}; -u32 R600_GS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x00000099, -}; -u32 R600_GS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000009C, -}; -u32 R600_GS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = { - 0xC0036E00, - 0x0000009F, -}; -#define R600_SAMPLER_state_cpm4 3 -u32 R600_SAMPLER_state_pm4[R600_SAMPLER_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, -}; - -/* R600_SAMPLER_BORDER */ -#define R600_SAMPLER_BORDER_header_cpm4 2 -u32 R600_PS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000900, -}; -u32 R600_PS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000904, -}; -u32 R600_PS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000908, -}; -u32 R600_PS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000090C, -}; -u32 R600_PS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000910, -}; -u32 R600_PS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000914, -}; -u32 R600_PS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000918, -}; -u32 R600_PS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000091C, -}; -u32 R600_PS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000920, -}; -u32 R600_PS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000924, -}; -u32 R600_PS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000928, -}; -u32 R600_PS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000092C, -}; -u32 R600_PS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000930, -}; -u32 R600_PS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000934, -}; -u32 R600_PS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000938, -}; -u32 R600_PS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000093C, -}; -u32 R600_PS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000940, -}; -u32 R600_PS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000944, -}; -u32 R600_VS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000980, -}; -u32 R600_VS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000984, -}; -u32 R600_VS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000988, -}; -u32 R600_VS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000098C, -}; -u32 R600_VS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000990, -}; -u32 R600_VS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000994, -}; -u32 R600_VS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000998, -}; -u32 R600_VS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x0000099C, -}; -u32 R600_VS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009A0, -}; -u32 R600_VS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009A4, -}; -u32 R600_VS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009A8, -}; -u32 R600_VS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009AC, -}; -u32 R600_VS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009B0, -}; -u32 R600_VS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009B4, -}; -u32 R600_VS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009B8, -}; -u32 R600_VS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009BC, -}; -u32 R600_VS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009C0, -}; -u32 R600_VS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x000009C4, -}; -u32 R600_GS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A00, -}; -u32 R600_GS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A04, -}; -u32 R600_GS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A08, -}; -u32 R600_GS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A0C, -}; -u32 R600_GS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A10, -}; -u32 R600_GS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A14, -}; -u32 R600_GS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A18, -}; -u32 R600_GS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A1C, -}; -u32 R600_GS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A20, -}; -u32 R600_GS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A24, -}; -u32 R600_GS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A28, -}; -u32 R600_GS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A2C, -}; -u32 R600_GS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A30, -}; -u32 R600_GS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A34, -}; -u32 R600_GS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A38, -}; -u32 R600_GS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A3C, -}; -u32 R600_GS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A40, -}; -u32 R600_GS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = { - 0xC0046800, - 0x00000A44, -}; -#define R600_SAMPLER_BORDER_state_cpm4 4 -u32 R600_SAMPLER_BORDER_state_pm4[R600_SAMPLER_BORDER_state_cpm4] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const struct radeon_type R600_types[] = { - {R600_CONFIG_header_pm4, R600_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0}, - {R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0}, - {R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0}, - {R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0}, - {R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0}, - {R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0}, - {R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0}, - {R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0}, - {R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0}, - {R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0}, - {R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0}, - {R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0}, - {R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL}, - {R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL}, - {R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL}, - {R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL}, - {R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL}, - {R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL}, - {R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL}, - {R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL}, - {R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL}, - {R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0}, - {R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0} -}; - -static const struct radeon_type R700_types[] = { - {R700_CONFIG_header_pm4, R700_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0}, - {R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0}, - {R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0}, - {R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0}, - {R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0}, - {R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0}, - {R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0}, - {R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0}, - {R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0}, - {R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0}, - {R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0}, - {R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0}, - {R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL}, - {R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL}, - {R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL}, - {R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL}, - {R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL}, - {R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL}, - {R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL}, - {R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL}, - {R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL}, - {R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0}, - {R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0}, - {R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0}, - {R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0}, - {R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0}, - {R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0} -}; diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h new file mode 100644 index 00000000000..b5365e4275a --- /dev/null +++ b/src/gallium/winsys/r600/drm/r600_states.h @@ -0,0 +1,562 @@ +/* + * Copyright © 2009 Jerome Glisse + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#ifndef R600_STATES_H +#define R600_STATES_H + +static const struct radeon_register R600_CONFIG_names[] = { + {0x00008C00, 0, 0, "SQ_CONFIG"}, + {0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"}, + {0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"}, + {0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"}, + {0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"}, + {0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"}, + {0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"}, + {0x00009508, 0, 0, "TA_CNTL_AUX"}, + {0x00009714, 0, 0, "VC_ENHANCE"}, + {0x00009830, 0, 0, "DB_DEBUG"}, + {0x00009838, 0, 0, "DB_WATERMARKS"}, + {0x00028350, 0, 0, "SX_MISC"}, + {0x000286C8, 0, 0, "SPI_THREAD_GROUPING"}, + {0x000287A0, 0, 0, "CB_SHADER_CONTROL"}, + {0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"}, + {0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"}, + {0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"}, + {0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"}, + {0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"}, + {0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"}, + {0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"}, + {0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"}, + {0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"}, + {0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"}, + {0x00028A14, 0, 0, "VGT_HOS_CNTL"}, + {0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"}, + {0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"}, + {0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"}, + {0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"}, + {0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"}, + {0x00028A2C, 0, 0, "VGT_GROUP_DECR"}, + {0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"}, + {0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"}, + {0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"}, + {0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"}, + {0x00028A40, 0, 0, "VGT_GS_MODE"}, + {0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"}, + {0x00028AB0, 0, 0, "VGT_STRMOUT_EN"}, + {0x00028AB4, 0, 0, "VGT_REUSE_OFF"}, + {0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"}, + {0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"}, +}; + +static const struct radeon_register R600_CB_CNTL_names[] = { + {0x00028120, 0, 0, "CB_CLEAR_RED"}, + {0x00028124, 0, 0, "CB_CLEAR_GREEN"}, + {0x00028128, 0, 0, "CB_CLEAR_BLUE"}, + {0x0002812C, 0, 0, "CB_CLEAR_ALPHA"}, + {0x0002823C, 0, 0, "CB_SHADER_MASK"}, + {0x00028238, 0, 0, "CB_TARGET_MASK"}, + {0x00028424, 0, 0, "CB_FOG_RED"}, + {0x00028428, 0, 0, "CB_FOG_GREEN"}, + {0x0002842C, 0, 0, "CB_FOG_BLUE"}, + {0x00028808, 0, 0, "CB_COLOR_CONTROL"}, + {0x00028C04, 0, 0, "PA_SC_AA_CONFIG"}, + {0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"}, + {0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"}, + {0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"}, + {0x00028C34, 0, 0, "CB_CLRCMP_SRC"}, + {0x00028C38, 0, 0, "CB_CLRCMP_DST"}, + {0x00028C3C, 0, 0, "CB_CLRCMP_MSK"}, + {0x00028C48, 0, 0, "PA_SC_AA_MASK"}, +}; + +static const struct radeon_register R600_RASTERIZER_names[] = { + {0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"}, + {0x00028810, 0, 0, "PA_CL_CLIP_CNTL"}, + {0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"}, + {0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"}, + {0x00028820, 0, 0, "PA_CL_NANINF_CNTL"}, + {0x00028A00, 0, 0, "PA_SU_POINT_SIZE"}, + {0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"}, + {0x00028A08, 0, 0, "PA_SU_LINE_CNTL"}, + {0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"}, + {0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"}, + {0x00028C00, 0, 0, "PA_SC_LINE_CNTL"}, + {0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"}, + {0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"}, + {0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"}, + {0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"}, + {0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"}, + {0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"}, + {0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"}, + {0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"}, + {0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"}, + {0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"}, +}; + +static const struct radeon_register R600_VIEWPORT_names[] = { + {0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"}, + {0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"}, + {0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"}, + {0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"}, + {0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"}, + {0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"}, + {0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"}, + {0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"}, + {0x00028818, 0, 0, "PA_CL_VTE_CNTL"}, +}; + +static const struct radeon_register R600_SCISSOR_names[] = { + {0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"}, + {0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"}, + {0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"}, + {0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"}, + {0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"}, + {0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"}, + {0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"}, + {0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"}, + {0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"}, + {0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"}, + {0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"}, + {0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"}, + {0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"}, + {0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"}, + {0x00028230, 0, 0, "PA_SC_EDGERULE"}, + {0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"}, + {0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"}, + {0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"}, + {0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"}, +}; + +static const struct radeon_register R600_BLEND_names[] = { + {0x00028414, 0, 0, "CB_BLEND_RED"}, + {0x00028418, 0, 0, "CB_BLEND_GREEN"}, + {0x0002841C, 0, 0, "CB_BLEND_BLUE"}, + {0x00028420, 0, 0, "CB_BLEND_ALPHA"}, + {0x00028780, 0, 0, "CB_BLEND0_CONTROL"}, + {0x00028784, 0, 0, "CB_BLEND1_CONTROL"}, + {0x00028788, 0, 0, "CB_BLEND2_CONTROL"}, + {0x0002878C, 0, 0, "CB_BLEND3_CONTROL"}, + {0x00028790, 0, 0, "CB_BLEND4_CONTROL"}, + {0x00028794, 0, 0, "CB_BLEND5_CONTROL"}, + {0x00028798, 0, 0, "CB_BLEND6_CONTROL"}, + {0x0002879C, 0, 0, "CB_BLEND7_CONTROL"}, + {0x00028804, 0, 0, "CB_BLEND_CONTROL"}, +}; + +static const struct radeon_register R600_DSA_names[] = { + {0x00028028, 0, 0, "DB_STENCIL_CLEAR"}, + {0x0002802C, 0, 0, "DB_DEPTH_CLEAR"}, + {0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"}, + {0x00028430, 0, 0, "DB_STENCILREFMASK"}, + {0x00028434, 0, 0, "DB_STENCILREFMASK_BF"}, + {0x00028438, 0, 0, "SX_ALPHA_REF"}, + {0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"}, + {0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"}, + {0x000286DC, 0, 0, "SPI_FOG_CNTL"}, + {0x00028800, 0, 0, "DB_DEPTH_CONTROL"}, + {0x0002880C, 0, 0, "DB_SHADER_CONTROL"}, + {0x00028D0C, 0, 0, "DB_RENDER_CONTROL"}, + {0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"}, + {0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"}, + {0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"}, + {0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"}, +}; + +static const struct radeon_register R600_VS_SHADER_names[] = { + {0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"}, + {0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"}, + {0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"}, + {0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"}, + {0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"}, + {0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"}, + {0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"}, + {0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"}, + {0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"}, + {0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"}, + {0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"}, + {0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"}, + {0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"}, + {0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"}, + {0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"}, + {0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"}, + {0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"}, + {0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"}, + {0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"}, + {0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"}, + {0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"}, + {0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"}, + {0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"}, + {0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"}, + {0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"}, + {0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"}, + {0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"}, + {0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"}, + {0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"}, + {0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"}, + {0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"}, + {0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"}, + {0x00028614, 0, 0, "SPI_VS_OUT_ID_0"}, + {0x00028618, 0, 0, "SPI_VS_OUT_ID_1"}, + {0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"}, + {0x00028620, 0, 0, "SPI_VS_OUT_ID_3"}, + {0x00028624, 0, 0, "SPI_VS_OUT_ID_4"}, + {0x00028628, 0, 0, "SPI_VS_OUT_ID_5"}, + {0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"}, + {0x00028630, 0, 0, "SPI_VS_OUT_ID_7"}, + {0x00028634, 0, 0, "SPI_VS_OUT_ID_8"}, + {0x00028638, 0, 0, "SPI_VS_OUT_ID_9"}, + {0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"}, + {0x00028858, 1, 0, "SQ_PGM_START_VS"}, + {0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"}, + {0x00028894, 1, 1, "SQ_PGM_START_FS"}, + {0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"}, + {0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"}, + {0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"}, +}; + +static const struct radeon_register R600_PS_SHADER_names[] = { + {0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"}, + {0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"}, + {0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"}, + {0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"}, + {0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"}, + {0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"}, + {0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"}, + {0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"}, + {0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"}, + {0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"}, + {0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"}, + {0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"}, + {0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"}, + {0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"}, + {0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"}, + {0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"}, + {0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"}, + {0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"}, + {0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"}, + {0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"}, + {0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"}, + {0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"}, + {0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"}, + {0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"}, + {0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"}, + {0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"}, + {0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"}, + {0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"}, + {0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"}, + {0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"}, + {0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"}, + {0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"}, + {0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"}, + {0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"}, + {0x000286D8, 0, 0, "SPI_INPUT_Z"}, + {0x00028840, 1, 0, "SQ_PGM_START_PS"}, + {0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"}, + {0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"}, + {0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"}, +}; + +static const struct radeon_register R600_PS_CONSTANT_names[] = { + {0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"}, + {0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"}, + {0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"}, + {0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"}, +}; + +static const struct radeon_register R600_VS_CONSTANT_names[] = { + {0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"}, + {0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"}, + {0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"}, + {0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"}, +}; + +static const struct radeon_register R600_UCP_names[] = { + {0x00028e20, 0, 0, "PA_CL_UCP0_X"}, + {0x00028e24, 0, 0, "PA_CL_UCP0_Y"}, + {0x00028e28, 0, 0, "PA_CL_UCP0_Z"}, + {0x00028e2c, 0, 0, "PA_CL_UCP0_W"}, +}; + +static const struct radeon_register R600_PS_RESOURCE_names[] = { + {0x00038000, 0, 0, "RESOURCE0_WORD0"}, + {0x00038004, 0, 0, "RESOURCE0_WORD1"}, + {0x00038008, 0, 0, "RESOURCE0_WORD2"}, + {0x0003800C, 0, 0, "RESOURCE0_WORD3"}, + {0x00038010, 0, 0, "RESOURCE0_WORD4"}, + {0x00038014, 0, 0, "RESOURCE0_WORD5"}, + {0x00038018, 0, 0, "RESOURCE0_WORD6"}, +}; + +static const struct radeon_register R600_VS_RESOURCE_names[] = { + {0x00039180, 0, 0, "RESOURCE160_WORD0"}, + {0x00039184, 0, 0, "RESOURCE160_WORD1"}, + {0x00039188, 0, 0, "RESOURCE160_WORD2"}, + {0x0003918C, 0, 0, "RESOURCE160_WORD3"}, + {0x00039190, 0, 0, "RESOURCE160_WORD4"}, + {0x00039194, 0, 0, "RESOURCE160_WORD5"}, + {0x00039198, 0, 0, "RESOURCE160_WORD6"}, +}; + +static const struct radeon_register R600_FS_RESOURCE_names[] = { + {0x0003A300, 0, 0, "RESOURCE320_WORD0"}, + {0x0003A304, 0, 0, "RESOURCE320_WORD1"}, + {0x0003A308, 0, 0, "RESOURCE320_WORD2"}, + {0x0003A30C, 0, 0, "RESOURCE320_WORD3"}, + {0x0003A310, 0, 0, "RESOURCE320_WORD4"}, + {0x0003A314, 0, 0, "RESOURCE320_WORD5"}, + {0x0003A318, 0, 0, "RESOURCE320_WORD6"}, +}; + +static const struct radeon_register R600_GS_RESOURCE_names[] = { + {0x0003A4C0, 0, 0, "RESOURCE336_WORD0"}, + {0x0003A4C4, 0, 0, "RESOURCE336_WORD1"}, + {0x0003A4C8, 0, 0, "RESOURCE336_WORD2"}, + {0x0003A4CC, 0, 0, "RESOURCE336_WORD3"}, + {0x0003A4D0, 0, 0, "RESOURCE336_WORD4"}, + {0x0003A4D4, 0, 0, "RESOURCE336_WORD5"}, + {0x0003A4D8, 0, 0, "RESOURCE336_WORD6"}, +}; + +static const struct radeon_register R600_PS_SAMPLER_names[] = { + {0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"}, + {0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"}, + {0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"}, +}; + +static const struct radeon_register R600_VS_SAMPLER_names[] = { + {0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"}, + {0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"}, + {0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"}, +}; + +static const struct radeon_register R600_GS_SAMPLER_names[] = { + {0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"}, + {0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"}, + {0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"}, +}; + +static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = { + {0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"}, + {0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"}, + {0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"}, + {0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = { + {0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"}, + {0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"}, + {0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"}, + {0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = { + {0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"}, + {0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"}, + {0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"}, + {0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"}, +}; + +static const struct radeon_register R600_CB0_names[] = { + {0x00028040, 1, 0, "CB_COLOR0_BASE"}, + {0x000280A0, 0, 0, "CB_COLOR0_INFO"}, + {0x00028060, 0, 0, "CB_COLOR0_SIZE"}, + {0x00028080, 0, 0, "CB_COLOR0_VIEW"}, + {0x000280E0, 1, 1, "CB_COLOR0_FRAG"}, + {0x000280C0, 1, 2, "CB_COLOR0_TILE"}, + {0x00028100, 0, 0, "CB_COLOR0_MASK"}, +}; + +static const struct radeon_register R600_CB1_names[] = { + {0x00028044, 1, 0, "CB_COLOR1_BASE"}, + {0x000280A4, 0, 0, "CB_COLOR1_INFO"}, + {0x00028064, 0, 0, "CB_COLOR1_SIZE"}, + {0x00028084, 0, 0, "CB_COLOR1_VIEW"}, + {0x000280E4, 1, 1, "CB_COLOR1_FRAG"}, + {0x000280C4, 1, 2, "CB_COLOR1_TILE"}, + {0x00028104, 0, 0, "CB_COLOR1_MASK"}, +}; + +static const struct radeon_register R600_CB2_names[] = { + {0x00028048, 1, 0, "CB_COLOR2_BASE"}, + {0x000280A8, 0, 0, "CB_COLOR2_INFO"}, + {0x00028068, 0, 0, "CB_COLOR2_SIZE"}, + {0x00028088, 0, 0, "CB_COLOR2_VIEW"}, + {0x000280E8, 1, 1, "CB_COLOR2_FRAG"}, + {0x000280C8, 1, 2, "CB_COLOR2_TILE"}, + {0x00028108, 0, 0, "CB_COLOR2_MASK"}, +}; + +static const struct radeon_register R600_CB3_names[] = { + {0x0002804C, 1, 0, "CB_COLOR3_BASE"}, + {0x000280AC, 0, 0, "CB_COLOR3_INFO"}, + {0x0002806C, 0, 0, "CB_COLOR3_SIZE"}, + {0x0002808C, 0, 0, "CB_COLOR3_VIEW"}, + {0x000280EC, 1, 1, "CB_COLOR3_FRAG"}, + {0x000280CC, 1, 2, "CB_COLOR3_TILE"}, + {0x0002810C, 0, 0, "CB_COLOR3_MASK"}, +}; + +static const struct radeon_register R600_CB4_names[] = { + {0x00028050, 1, 0, "CB_COLOR4_BASE"}, + {0x000280B0, 0, 0, "CB_COLOR4_INFO"}, + {0x00028070, 0, 0, "CB_COLOR4_SIZE"}, + {0x00028090, 0, 0, "CB_COLOR4_VIEW"}, + {0x000280F0, 1, 1, "CB_COLOR4_FRAG"}, + {0x000280D0, 1, 2, "CB_COLOR4_TILE"}, + {0x00028110, 0, 0, "CB_COLOR4_MASK"}, +}; + +static const struct radeon_register R600_CB5_names[] = { + {0x00028054, 1, 0, "CB_COLOR5_BASE"}, + {0x000280B4, 0, 0, "CB_COLOR5_INFO"}, + {0x00028074, 0, 0, "CB_COLOR5_SIZE"}, + {0x00028094, 0, 0, "CB_COLOR5_VIEW"}, + {0x000280F4, 1, 1, "CB_COLOR5_FRAG"}, + {0x000280D4, 1, 2, "CB_COLOR5_TILE"}, + {0x00028114, 0, 0, "CB_COLOR5_MASK"}, +}; + +static const struct radeon_register R600_CB6_names[] = { + {0x00028058, 1, 0, "CB_COLOR6_BASE"}, + {0x000280B8, 0, 0, "CB_COLOR6_INFO"}, + {0x00028078, 0, 0, "CB_COLOR6_SIZE"}, + {0x00028098, 0, 0, "CB_COLOR6_VIEW"}, + {0x000280F8, 1, 1, "CB_COLOR6_FRAG"}, + {0x000280D8, 1, 2, "CB_COLOR6_TILE"}, + {0x00028118, 0, 0, "CB_COLOR6_MASK"}, +}; + +static const struct radeon_register R600_CB7_names[] = { + {0x0002805C, 1, 0, "CB_COLOR7_BASE"}, + {0x000280BC, 0, 0, "CB_COLOR7_INFO"}, + {0x0002807C, 0, 0, "CB_COLOR7_SIZE"}, + {0x0002809C, 0, 0, "CB_COLOR7_VIEW"}, + {0x000280FC, 1, 1, "CB_COLOR7_FRAG"}, + {0x000280DC, 1, 2, "CB_COLOR7_TILE"}, + {0x0002811C, 0, 0, "CB_COLOR7_MASK"}, +}; + +static const struct radeon_register R600_DB_names[] = { + {0x0002800C, 1, 0, "DB_DEPTH_BASE"}, + {0x00028000, 0, 0, "DB_DEPTH_SIZE"}, + {0x00028004, 0, 0, "DB_DEPTH_VIEW"}, + {0x00028010, 0, 0, "DB_DEPTH_INFO"}, + {0x00028D24, 0, 0, "DB_HTILE_SURFACE"}, + {0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"}, +}; + +static const struct radeon_register R600_VGT_names[] = { + {0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, + {0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, + {0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, + {0x00028408, 0, 0, "VGT_INDX_OFFSET"}, + {0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"}, + {0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, + {0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, + {0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, + {0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, + {0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, + {0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, +}; + +static const struct radeon_register R600_DRAW_names[] = { + {0x00008970, 0, 0, "VGT_NUM_INDICES"}, + {0x000287E4, 0, 0, "VGT_DMA_BASE_HI"}, + {0x000287E8, 1, 0, "VGT_DMA_BASE"}, + {0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, +}; + +static const struct radeon_register R600_VGT_EVENT_names[] = { + {0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, +}; + +static struct radeon_type R600_types[] = { + { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names}, + { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, + { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, + { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, + { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, + { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, + { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, + { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, + { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, + { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, + { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, + { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, + { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, + { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, + { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, + { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, + { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, + { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, + { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, + { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, + { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, + { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names}, + { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names}, + { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names}, + { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names}, + { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names}, + { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names}, + { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names}, + { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names}, + { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names}, + { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names}, + { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names}, + { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names}, + { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, + { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, +}; + +static struct radeon_type R700_types[] = { + { 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names}, + { 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names}, + { 128, 2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names}, + { 128, 3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names}, + { 128, 4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names}, + { 128, 5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names}, + { 128, 6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names}, + { 128, 7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names}, + { 128, 8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names}, + { 128, 9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names}, + { 128, 265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names}, + { 128, 521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names}, + { 128, 681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names}, + { 128, 841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names}, + { 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names}, + { 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names}, + { 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names}, + { 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names}, + { 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names}, + { 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names}, + { 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names}, + { 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names}, + { 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names}, + { 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names}, + { 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names}, + { 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names}, + { 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names}, + { 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names}, + { 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names}, + { 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names}, + { 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names}, + { 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names}, + { 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names}, + { 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names}, + { 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names}, +}; + +#endif diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c index 2b16e3ce884..80b0a1d3972 100644 --- a/src/gallium/winsys/r600/drm/radeon.c +++ b/src/gallium/winsys/r600/drm/radeon.c @@ -153,3 +153,47 @@ struct radeon *radeon_decref(struct radeon *radeon) free(radeon); return NULL; } + +int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id) +{ + unsigned i, j; + + for (i = 0; i < radeon->ntype; i++) { + if (radeon->type[i].range_start) { + if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) { + *typeid = i; + j = offset - radeon->type[i].range_start; + j /= radeon->type[i].stride; + *stateid = radeon->type[i].id + j; + *id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4; + return 0; + } + } else { + for (j = 0; j < radeon->type[i].nstates; j++) { + if (radeon->type[i].regs[j].offset == offset) { + *typeid = i; + *stateid = radeon->type[i].id; + *id = j; + return 0; + } + } + } + } + fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset); + return -EINVAL; +} + +unsigned radeon_type_from_id(struct radeon *radeon, unsigned id) +{ + unsigned i; + + for (i = 0; i < radeon->ntype - 1; i++) { + if (radeon->type[i].id == id) + return i; + if (id > radeon->type[i].id && id < radeon->type[i + 1].id) + return i; + } + if (radeon->type[i].id == id) + return i; + return -1; +} diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c index b8ba9b552df..bd050c4cf90 100644 --- a/src/gallium/winsys/r600/drm/radeon_ctx.c +++ b/src/gallium/winsys/r600/drm/radeon_ctx.c @@ -26,40 +26,54 @@ #include #include #include -#include #include "radeon_priv.h" #include "radeon_drm.h" #include "bof.h" -static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned state_id) +int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo) { - ctx->bo[ctx->nbo].bo = bo; - ctx->bo[ctx->nbo].bo_flushed = 0; - ctx->bo[ctx->nbo].state_id = state_id; + void *ptr; + + ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1)); + if (ptr == NULL) { + return -ENOMEM; + } + ctx->bo = ptr; + ctx->bo[ctx->nbo] = bo; ctx->nbo++; return 0; } -void radeon_ctx_clear(struct radeon_ctx *ctx) +struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc) { + struct radeon_cs_reloc *greloc; unsigned i; - /* FIXME somethings is wrong, it should be safe to - * delete bo here, kernel should postpone bo deletion - * until bo is no longer referenced by cs (through the - * fence association) - */ - for (i = 0; i < 50; i++) { - usleep(10); + greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4); + for (i = 0; i < ctx->nbo; i++) { + if (ctx->bo[i]->handle == greloc->handle) { + return radeon_bo_incref(ctx->radeon, ctx->bo[i]); + } } + fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo); + return NULL; +} + +void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement) +{ + struct radeon_cs_reloc *greloc; + unsigned i; + + placement[0] = 0; + placement[1] = 0; + greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4); for (i = 0; i < ctx->nbo; i++) { - ctx->bo[i].bo = radeon_bo_decref(ctx->radeon, ctx->bo[i].bo); + if (ctx->bo[i]->handle == greloc->handle) { + placement[0] = greloc->read_domain | greloc->write_domain; + placement[1] = placement[0]; + return; + } } - ctx->id = 0; - ctx->npm4 = RADEON_CTX_MAX_PM4; - ctx->nreloc = 0; - ctx->nbo = 0; - memset(ctx->state_crc32, 0, ctx->radeon->nstate * 4); } struct radeon_ctx *radeon_ctx(struct radeon *radeon) @@ -72,25 +86,6 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon) if (ctx == NULL) return NULL; ctx->radeon = radeon_incref(radeon); - ctx->max_bo = 4096; - ctx->max_reloc = 4096; - ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4); - if (ctx->pm4 == NULL) { - return radeon_ctx_decref(ctx); - } - ctx->state_crc32 = malloc(ctx->radeon->nstate * 4); - if (ctx->state_crc32 == NULL) { - return radeon_ctx_decref(ctx); - } - ctx->bo = malloc(ctx->max_bo * sizeof(struct radeon_ctx_bo)); - if (ctx->bo == NULL) { - return radeon_ctx_decref(ctx); - } - ctx->reloc = malloc(ctx->max_reloc * sizeof(struct radeon_cs_reloc)); - if (ctx->reloc == NULL) { - return radeon_ctx_decref(ctx); - } - radeon_ctx_clear(ctx); return ctx; } @@ -102,33 +97,31 @@ struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx) struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx) { + unsigned i; + if (ctx == NULL) return NULL; if (--ctx->refcount > 0) { return NULL; } + for (i = 0; i < ctx->ndraw; i++) { + ctx->draw[i] = radeon_draw_decref(ctx->draw[i]); + } + for (i = 0; i < ctx->nbo; i++) { + ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]); + } ctx->radeon = radeon_decref(ctx->radeon); + free(ctx->state); + free(ctx->draw); free(ctx->bo); free(ctx->pm4); free(ctx->reloc); - free(ctx->state_crc32); memset(ctx, 0, sizeof(*ctx)); free(ctx); return NULL; } -static int radeon_ctx_bo_id(struct radeon_ctx *ctx, struct radeon_bo *bo) -{ - unsigned i; - - for (i = 0; i < ctx->nbo; i++) { - if (bo == ctx->bo[i].bo) - return i; - } - return -1; -} - static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state) { unsigned i, j; @@ -138,15 +131,12 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat return 0; for (i = 0; i < state->nbo; i++) { for (j = 0; j < ctx->nbo; j++) { - if (state->bo[i] == ctx->bo[j].bo) + if (state->bo[i] == ctx->bo[j]) break; } if (j == ctx->nbo) { - if (ctx->nbo >= ctx->max_bo) { - return -EBUSY; - } radeon_bo_incref(ctx->radeon, state->bo[i]); - r = radeon_ctx_set_bo_new(ctx, state->bo[i], state->id); + r = radeon_ctx_set_bo_new(ctx, state->bo[i]); if (r) return r; } @@ -154,6 +144,7 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat return 0; } + int radeon_ctx_submit(struct radeon_ctx *ctx) { struct drm_radeon_cs drmib; @@ -161,17 +152,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx) uint64_t chunk_array[2]; int r = 0; - if (!ctx->id) + if (!ctx->cpm4) return 0; #if 0 - for (r = 0; r < ctx->id; r++) { + for (r = 0; r < ctx->cpm4; r++) { fprintf(stderr, "0x%08X\n", ctx->pm4[r]); } #endif drmib.num_chunks = 2; drmib.chunks = (uint64_t)(uintptr_t)chunk_array; chunks[0].chunk_id = RADEON_CHUNK_ID_IB; - chunks[0].length_dw = ctx->id; + chunks[0].length_dw = ctx->cpm4; chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4; chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; @@ -185,10 +176,11 @@ int radeon_ctx_submit(struct radeon_ctx *ctx) return r; } -int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, +static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned id, unsigned *placement) { unsigned i; + struct radeon_cs_reloc *ptr; for (i = 0; i < ctx->nreloc; i++) { if (ctx->reloc[i].handle == bo->handle) { @@ -196,13 +188,14 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, return 0; } } - if (ctx->nreloc >= ctx->max_reloc) { - return -EBUSY; - } - ctx->reloc[ctx->nreloc].handle = bo->handle; - ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1]; - ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1]; - ctx->reloc[ctx->nreloc].flags = 0; + ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1)); + if (ptr == NULL) + return -ENOMEM; + ctx->reloc = ptr; + ptr[ctx->nreloc].handle = bo->handle; + ptr[ctx->nreloc].read_domain = placement[0] | placement [1]; + ptr[ctx->nreloc].write_domain = placement[0] | placement [1]; + ptr[ctx->nreloc].flags = 0; ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4; ctx->nreloc++; return 0; @@ -210,90 +203,75 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state) { - unsigned i, rid, cid; - u32 flags; - int r, bo_id[4]; + unsigned i, rid, bid, cid; + int r; if (state == NULL) return 0; - for (i = 0; i < state->nbo; i++) { - bo_id[i] = radeon_ctx_bo_id(ctx, state->bo[i]); - if (bo_id[i] < 0) { - return -EINVAL; - } - flags = (~ctx->bo[bo_id[i]].bo_flushed) & ctx->radeon->type[state->id].flush_flags; - if (flags) { - r = ctx->radeon->bo_flush(ctx, state->bo[i], flags, &state->placement[i * 2]); - if (r) { - return r; - } - } - ctx->bo[bo_id[i]].bo_flushed |= ctx->radeon->type[state->id].flush_flags; - } - if ((ctx->radeon->type[state->id].header_cpm4 + state->cpm4) > ctx->npm4) { - /* need to flush */ - return -EBUSY; - } - memcpy(&ctx->pm4[ctx->id], ctx->radeon->type[state->id].header_pm4, ctx->radeon->type[state->id].header_cpm4 * 4); - ctx->id += ctx->radeon->type[state->id].header_cpm4; - ctx->npm4 -= ctx->radeon->type[state->id].header_cpm4; - memcpy(&ctx->pm4[ctx->id], state->states, state->cpm4 * 4); - for (i = 0; i < state->nbo; i++) { + memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4); + for (i = 0; i < state->nreloc; i++) { rid = state->reloc_pm4_id[i]; + bid = state->reloc_bo_id[i]; cid = ctx->id + rid; - r = radeon_ctx_reloc(ctx, state->bo[i], cid, - &state->placement[i * 2]); + r = radeon_ctx_reloc(ctx, state->bo[bid], cid, + &state->placement[bid * 2]); if (r) { - fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->id); + fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type); return r; } } ctx->id += state->cpm4; - ctx->npm4 -= state->cpm4; - for (i = 0; i < state->nbo; i++) { - ctx->bo[bo_id[i]].bo_flushed &= ~ctx->radeon->type[state->id].dirty_flags; - } return 0; } int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state) { - unsigned ndw = 0; + void *tmp; int r = 0; + /* !!! ONLY ACCEPT QUERY STATE HERE !!! */ + if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) { + return -EINVAL; + } r = radeon_state_pm4(state); if (r) return r; - - /* !!! ONLY ACCEPT QUERY STATE HERE !!! */ - ndw = state->cpm4 + ctx->radeon->type[state->id].header_cpm4; - switch (state->id) { - case R600_QUERY_BEGIN: - /* account QUERY_END at same time of QUERY_BEGIN so we know we - * have room left for QUERY_END - */ - if ((ndw * 2) > ctx->npm4) { - /* need to flush */ - return -EBUSY; - } - ctx->npm4 -= ndw; - break; - case R600_QUERY_END: - /* add again ndw from previous accounting */ - ctx->npm4 += ndw; - break; - default: + if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) { + /* need to flush */ + return -EBUSY; + } + if (state->cpm4 >= RADEON_CTX_MAX_PM4) { + fprintf(stderr, "%s single state too big %d, max %d\n", + __func__, state->cpm4, RADEON_CTX_MAX_PM4); return -EINVAL; } - - return radeon_ctx_state_schedule(ctx, state); + tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*)); + if (tmp == NULL) + return -ENOMEM; + ctx->state = tmp; + ctx->state[ctx->nstate++] = radeon_state_incref(state); + /* BEGIN/END query are balanced in the same cs so account for END + * END query when scheduling BEGIN query + */ + if (state->type == R600_QUERY_BEGIN_TYPE) { + ctx->draw_cpm4 += state->cpm4 * 2; + } + return 0; } -int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw) { - unsigned i, previous_id; + struct radeon_draw *pdraw = NULL; + struct radeon_draw **ndraw; + struct radeon_state *nstate, *ostate; + unsigned cpm4, i, cstate; + void *tmp; int r = 0; + ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1)); + if (ndraw == NULL) + return -ENOMEM; + ctx->draw = ndraw; for (i = 0; i < draw->nstate; i++) { r = radeon_ctx_state_bo(ctx, draw->state[i]); if (r) @@ -307,17 +285,76 @@ int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) __func__, draw->cpm4, RADEON_CTX_MAX_PM4); return -EINVAL; } - previous_id = ctx->id; - for (i = 0; i < draw->nstate; i++) { - /* FIXME always force draw state to schedule */ - if (draw->state[i] && draw->state[i]->pm4_crc != ctx->state_crc32[draw->state[i]->id]) { - r = radeon_ctx_state_schedule(ctx, draw->state[i]); - if (r) { - ctx->id = previous_id; - return r; + tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*)); + if (tmp == NULL) + return -ENOMEM; + ctx->state = tmp; + pdraw = ctx->cdraw; + for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) { + nstate = draw->state[i]; + if (nstate) { + if (pdraw && pdraw->state[i]) { + ostate = pdraw->state[i]; + if (ostate->pm4_crc != nstate->pm4_crc) { + ctx->state[cstate++] = nstate; + cpm4 += nstate->cpm4; + } + } else { + ctx->state[cstate++] = nstate; + cpm4 += nstate->cpm4; } } } + /* The last state is the draw state always add it */ + if (draw->state[i] == NULL) { + fprintf(stderr, "%s no draw command\n", __func__); + return -EINVAL; + } + ctx->state[cstate++] = draw->state[i]; + cpm4 += draw->state[i]->cpm4; + if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) { + /* need to flush */ + return -EBUSY; + } + ctx->draw_cpm4 += cpm4; + ctx->nstate = cstate; + ctx->draw[ctx->ndraw++] = draw; + ctx->cdraw = draw; + return 0; +} + +int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw) +{ + int r; + + radeon_draw_incref(draw); + r = radeon_ctx_set_draw_new(ctx, draw); + if (r) + radeon_draw_decref(draw); + return r; +} + +int radeon_ctx_pm4(struct radeon_ctx *ctx) +{ + unsigned i; + int r; + + free(ctx->pm4); + ctx->cpm4 = 0; + ctx->pm4 = malloc(ctx->draw_cpm4 * 4); + if (ctx->pm4 == NULL) + return -EINVAL; + for (i = 0, ctx->id = 0; i < ctx->nstate; i++) { + r = radeon_ctx_state_schedule(ctx, ctx->state[i]); + if (r) + return r; + } + if (ctx->id != ctx->draw_cpm4) { + fprintf(stderr, "%s miss predicted pm4 size %d for %d\n", + __func__, ctx->draw_cpm4, ctx->id); + return -EINVAL; + } + ctx->cpm4 = ctx->draw_cpm4; return 0; } @@ -347,8 +384,8 @@ printf("%d relocs\n", ctx->nreloc); bof_decref(blob); blob = NULL; /* dump cs */ -printf("%d pm4\n", ctx->id); - blob = bof_blob(ctx->id * 4, ctx->pm4); +printf("%d pm4\n", ctx->cpm4); + blob = bof_blob(ctx->cpm4 * 4, ctx->pm4); if (blob == NULL) goto out_err; if (bof_object_set(root, "pm4", blob)) @@ -363,23 +400,23 @@ printf("%d pm4\n", ctx->id); bo = bof_object(); if (bo == NULL) goto out_err; - size = bof_int32(ctx->bo[i].bo->size); + size = bof_int32(ctx->bo[i]->size); if (size == NULL) goto out_err; if (bof_object_set(bo, "size", size)) goto out_err; bof_decref(size); size = NULL; - handle = bof_int32(ctx->bo[i].bo->handle); + handle = bof_int32(ctx->bo[i]->handle); if (handle == NULL) goto out_err; if (bof_object_set(bo, "handle", handle)) goto out_err; bof_decref(handle); handle = NULL; - radeon_bo_map(ctx->radeon, ctx->bo[i].bo); - blob = bof_blob(ctx->bo[i].bo->size, ctx->bo[i].bo->data); - radeon_bo_unmap(ctx->radeon, ctx->bo[i].bo); + radeon_bo_map(ctx->radeon, ctx->bo[i]); + blob = bof_blob(ctx->bo[i]->size, ctx->bo[i]->data); + radeon_bo_unmap(ctx->radeon, ctx->bo[i]); if (blob == NULL) goto out_err; if (bof_object_set(bo, "data", blob)) diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c index 1b4e557f280..4413ed79fbd 100644 --- a/src/gallium/winsys/r600/drm/radeon_draw.c +++ b/src/gallium/winsys/r600/drm/radeon_draw.c @@ -76,6 +76,8 @@ int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state) { if (state == NULL) return 0; + if (state->type >= draw->radeon->ntype) + return -EINVAL; draw->state[state->id] = radeon_state_decref(draw->state[state->id]); draw->state[state->id] = state; return 0; @@ -100,7 +102,6 @@ int radeon_draw_check(struct radeon_draw *draw) for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) { if (draw->state[i]) { draw->cpm4 += draw->state[i]->cpm4; - draw->cpm4 += draw->radeon->type[draw->state[i]->id].header_cpm4; } } return 0; diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h index 469a5dce012..96c0d060f7e 100644 --- a/src/gallium/winsys/r600/drm/radeon_priv.h +++ b/src/gallium/winsys/r600/drm/radeon_priv.h @@ -30,26 +30,34 @@ struct radeon_ctx; * radeon functions */ typedef int (*radeon_state_pm4_t)(struct radeon_state *state); +struct radeon_register { + unsigned offset; + unsigned need_reloc; + unsigned bo_id; + char name[64]; +}; struct radeon_type { - const u32 *header_pm4; - const u32 header_cpm4; - const u32 *state_pm4; - const u32 state_cpm4; - const u32 flush_flags; - const u32 dirty_flags; + unsigned npm4; + unsigned id; + unsigned range_start; + unsigned range_end; + unsigned stride; + unsigned immediate; + char name[64]; + unsigned nstates; + radeon_state_pm4_t pm4; + const struct radeon_register *regs; }; -typedef int (*radeon_ctx_bo_flush_t)(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement); - struct radeon { int fd; int refcount; unsigned device; unsigned family; unsigned nstate; + unsigned ntype; const struct radeon_type *type; - radeon_ctx_bo_flush_t bo_flush; }; extern struct radeon *radeon_new(int fd, unsigned device); @@ -60,9 +68,12 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2); extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id); extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id); + +int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo); +struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc); +void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement); +int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw); int radeon_ctx_draw(struct radeon_ctx *ctx); -int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo, - unsigned id, unsigned *placement); /* * r600/r700 context functions @@ -79,6 +90,7 @@ extern int radeon_state_register_set(struct radeon_state *state, unsigned offset extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state); extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate); extern int radeon_state_pm4_generic(struct radeon_state *state); +extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id); /* * radeon draw functions diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c index c60b12ef67c..308288557a4 100644 --- a/src/gallium/winsys/r600/drm/radeon_state.c +++ b/src/gallium/winsys/r600/drm/radeon_state.c @@ -32,29 +32,52 @@ /* * state core functions */ -struct radeon_state *radeon_state(struct radeon *radeon, u32 id) +struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id) { struct radeon_state *state; + if (type > radeon->ntype) { + fprintf(stderr, "%s invalid type %d\n", __func__, type); + return NULL; + } + if (id > radeon->nstate) { + fprintf(stderr, "%s invalid state id %d\n", __func__, id); + return NULL; + } state = calloc(1, sizeof(*state)); if (state == NULL) return NULL; state->radeon = radeon; + state->type = type; state->id = id; state->refcount = 1; - state->cpm4 = radeon->type[id].state_cpm4; - memcpy(state->states, radeon->type[id].state_pm4, radeon->type[id].state_cpm4 * 4); + state->npm4 = radeon->type[type].npm4; + state->nstates = radeon->type[type].nstates; + state->states = calloc(1, state->nstates * 4); + state->pm4 = calloc(1, radeon->type[type].npm4 * 4); + if (state->states == NULL || state->pm4 == NULL) { + radeon_state_decref(state); + return NULL; + } return state; } struct radeon_state *radeon_state_duplicate(struct radeon_state *state) { - struct radeon_state *nstate = radeon_state(state->radeon, state->id); + struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id); unsigned i; if (state == NULL) return NULL; - *nstate = *state; + nstate->cpm4 = state->cpm4; + nstate->nbo = state->nbo; + nstate->nreloc = state->nreloc; + memcpy(nstate->states, state->states, state->nstates * 4); + memcpy(nstate->pm4, state->pm4, state->npm4 * 4); + memcpy(nstate->placement, state->placement, 8 * 4); + memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4); + memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4); + memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4); for (i = 0; i < state->nbo; i++) { nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]); } @@ -79,6 +102,9 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state) for (i = 0; i < state->nbo; i++) { state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]); } + free(state->immd); + free(state->states); + free(state->pm4); memset(state, 0, sizeof(*state)); free(state); return NULL; @@ -119,8 +145,24 @@ static u32 crc32(void *d, size_t len) int radeon_state_pm4(struct radeon_state *state) { - if (state == NULL) + int r; + + if (state == NULL || state->cpm4) return 0; - state->pm4_crc = crc32(state->states, state->cpm4 * 4); + r = state->radeon->type[state->type].pm4(state); + if (r) { + fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n", + __func__, state->type, state->id); + return r; + } + state->pm4_crc = crc32(state->pm4, state->cpm4 * 4); + return 0; +} + +int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id) +{ + state->reloc_pm4_id[state->nreloc] = id; + state->reloc_bo_id[state->nreloc] = bo_id; + state->nreloc++; return 0; }