From: Jim Wilson Date: Tue, 18 Nov 1997 23:42:00 +0000 (+0000) Subject: Fix gcc2 irix5 c-torture failures, EH/large frame errors X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=218c2cdbed7d708d93afff81c11a3f5f0b933ef7;p=gcc.git Fix gcc2 irix5 c-torture failures, EH/large frame errors Fix gcc2 irix5 c-torture failures, EH/large frame errors * mips/mips.c (save_restore_insns): If gp_offset or fp_offset are large_int, emit two insns instead of one splitable insn. * dwarf2out.c (dwarf2out_frame_debug): When set cfa_store_offset from cfa_temp_value, use cfa_offset. Add assert checking that cfa_reg is SP. From-SVN: r16573 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eea0bf05b4c..e35094a81f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +Tue Nov 18 15:39:59 1997 Jim Wilson + + * mips/mips.c (save_restore_insns): If gp_offset or fp_offset are + large_int, emit two insns instead of one splitable insn. + * dwarf2out.c (dwarf2out_frame_debug): When set cfa_store_offset + from cfa_temp_value, use cfa_offset. Add assert checking that + cfa_reg is SP. + Mon Nov 17 15:35:38 1997 Tom Tromey * cccp.c (deps_output): Properly quote file names for make. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 2d6984b8737..706a9bfe7bf 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -5011,9 +5011,32 @@ save_restore_insns (store_p, large_reg, large_offset, file) base_offset = gp_offset; if (file == (FILE *)0) { - insn = emit_move_insn (base_reg_rtx, GEN_INT (gp_offset)); - if (store_p) - RTX_FRAME_RELATED_P (insn) = 1; + rtx gp_offset_rtx = GEN_INT (gp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (gp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (gp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (gp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, gp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + if (TARGET_LONG64) insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx)); else @@ -5131,7 +5154,32 @@ save_restore_insns (store_p, large_reg, large_offset, file) base_offset = fp_offset; if (file == (FILE *)0) { - insn = emit_move_insn (base_reg_rtx, GEN_INT (fp_offset)); + rtx fp_offset_rtx = GEN_INT (fp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (fp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (fp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (fp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, fp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + if (store_p) RTX_FRAME_RELATED_P (insn) = 1; if (TARGET_LONG64) diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index dbb0049075d..db472755bb2 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -1194,8 +1194,10 @@ dwarf2out_frame_debug (insn) if (GET_CODE (XEXP (src, 0)) != REG || REGNO (XEXP (src, 0)) != cfa_temp_reg) abort (); + if (cfa_reg != STACK_POINTER_REGNUM) + abort (); cfa_store_reg = REGNO (dest); - cfa_store_offset -= cfa_temp_value; + cfa_store_offset = cfa_offset - cfa_temp_value; } break;