From: Jason Ekstrand Date: Fri, 19 Aug 2016 07:54:56 +0000 (-0700) Subject: i965/blorp: Get rid of brw_context X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2191f5cb7ed3205f8110ca989e13ade517084171;p=mesa.git i965/blorp: Get rid of brw_context This commit switches all of blorp from taking a brw_context to taking a blorp_context and, where useful, a void *batch. In the GL driver, we only have one active batch at a time so the brw_context *is* the batch but in Vulkan, batch will point to the anv_cmd_buffer in which we are building instructions. Signed-off-by: Jason Ekstrand Reviewed-by: Topi Pohjolainen --- diff --git a/src/mesa/drivers/dri/i965/blorp.c b/src/mesa/drivers/dri/i965/blorp.c index e81b9ebc366..deba011ac55 100644 --- a/src/mesa/drivers/dri/i965/blorp.c +++ b/src/mesa/drivers/dri/i965/blorp.c @@ -59,7 +59,7 @@ blorp_batch_finish(struct blorp_batch *batch) } void -brw_blorp_surface_info_init(struct brw_context *brw, +brw_blorp_surface_info_init(struct blorp_context *blorp, struct brw_blorp_surface_info *info, const struct brw_blorp_surf *surf, unsigned int level, unsigned int layer, @@ -91,7 +91,7 @@ brw_blorp_surface_info_init(struct brw_context *brw, } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) { assert(surf->surf->format == ISL_FORMAT_R8_UINT); /* Prior to Broadwell, we can't render to R8_UINT */ - if (brw->gen < 8) + if (blorp->isl_dev->info->gen < 8) format = ISL_FORMAT_R8_UNORM; } @@ -237,15 +237,16 @@ brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir } void -blorp_gen6_hiz_op(struct brw_context *brw, struct brw_blorp_surf *surf, - unsigned level, unsigned layer, enum gen6_hiz_op op) +blorp_gen6_hiz_op(struct blorp_batch *batch, + struct brw_blorp_surf *surf, unsigned level, unsigned layer, + enum gen6_hiz_op op) { struct brw_blorp_params params; brw_blorp_params_init(¶ms); params.hiz_op = op; - brw_blorp_surface_info_init(brw, ¶ms.depth, surf, level, layer, + brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, surf, level, layer, surf->surf->format, true); /* Align the rectangle primitive to 8x4 pixels. @@ -303,8 +304,5 @@ blorp_gen6_hiz_op(struct brw_context *brw, struct brw_blorp_surf *surf, unreachable("not reached"); } - struct blorp_batch batch; - blorp_batch_init(&brw->blorp, &batch, brw); - brw->blorp.exec(&batch, ¶ms); - blorp_batch_finish(&batch); + batch->blorp->exec(batch, ¶ms); } diff --git a/src/mesa/drivers/dri/i965/blorp.h b/src/mesa/drivers/dri/i965/blorp.h index 865ac00aac9..0f0a14ef410 100644 --- a/src/mesa/drivers/dri/i965/blorp.h +++ b/src/mesa/drivers/dri/i965/blorp.h @@ -98,7 +98,7 @@ struct brw_blorp_surf }; void -brw_blorp_blit(struct brw_context *brw, +brw_blorp_blit(struct blorp_batch *batch, const struct brw_blorp_surf *src_surf, unsigned src_level, unsigned src_layer, enum isl_format src_format, int src_swizzle, @@ -112,13 +112,13 @@ brw_blorp_blit(struct brw_context *brw, uint32_t filter, bool mirror_x, bool mirror_y); void -blorp_fast_clear(struct brw_context *brw, +blorp_fast_clear(struct blorp_batch *batch, const struct brw_blorp_surf *surf, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1); void -blorp_clear(struct brw_context *brw, +blorp_clear(struct blorp_batch *batch, const struct brw_blorp_surf *surf, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, @@ -126,12 +126,13 @@ blorp_clear(struct brw_context *brw, bool color_write_disable[4]); void -brw_blorp_ccs_resolve(struct brw_context *brw, struct brw_blorp_surf *surf, - enum isl_format format); +brw_blorp_ccs_resolve(struct blorp_batch *batch, + struct brw_blorp_surf *surf, enum isl_format format); void -blorp_gen6_hiz_op(struct brw_context *brw, struct brw_blorp_surf *surf, - unsigned level, unsigned layer, enum gen6_hiz_op op); +blorp_gen6_hiz_op(struct blorp_batch *batch, + struct brw_blorp_surf *surf, unsigned level, unsigned layer, + enum gen6_hiz_op op); #ifdef __cplusplus } /* end extern "C" */ diff --git a/src/mesa/drivers/dri/i965/blorp_blit.c b/src/mesa/drivers/dri/i965/blorp_blit.c index 598f9d788ad..c5f8272cfd0 100644 --- a/src/mesa/drivers/dri/i965/blorp_blit.c +++ b/src/mesa/drivers/dri/i965/blorp_blit.c @@ -988,9 +988,10 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos, * of samples). */ static nir_shader * -brw_blorp_build_nir_shader(struct brw_context *brw, +brw_blorp_build_nir_shader(struct blorp_context *blorp, const struct brw_blorp_blit_prog_key *key) { + const struct brw_device_info *devinfo = blorp->isl_dev->info; nir_ssa_def *src_pos, *dst_pos, *color; /* Sanity checks */ @@ -1043,7 +1044,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw, /* Render target and texture hardware don't support W tiling until Gen8. */ const bool rt_tiled_w = false; - const bool tex_tiled_w = brw->gen >= 8 && key->src_tiled_w; + const bool tex_tiled_w = devinfo->gen >= 8 && key->src_tiled_w; /* The address that data will be written to is determined by the * coordinates supplied to the WM thread and the tiling and sample count of @@ -1109,7 +1110,7 @@ brw_blorp_build_nir_shader(struct brw_context *brw, */ src_pos = nir_f2i(&b, nir_channels(&b, src_pos, 0x3)); - if (brw->gen == 6) { + if (devinfo->gen == 6) { /* Because gen6 only supports 4x interleved MSAA, we can do all the * blending we need with a single linear-interpolated texture lookup * at the center of the sample. The texture coordinates to be odd @@ -1191,12 +1192,12 @@ brw_blorp_build_nir_shader(struct brw_context *brw, } static void -brw_blorp_get_blit_kernel(struct brw_context *brw, +brw_blorp_get_blit_kernel(struct blorp_context *blorp, struct brw_blorp_params *params, const struct brw_blorp_blit_prog_key *prog_key) { - if (brw->blorp.lookup_shader(&brw->blorp, prog_key, sizeof(*prog_key), - ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) + if (blorp->lookup_shader(blorp, prog_key, sizeof(*prog_key), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) return; const unsigned *program; @@ -1206,7 +1207,7 @@ brw_blorp_get_blit_kernel(struct brw_context *brw, /* Try and compile with NIR first. If that fails, fall back to the old * method of building shaders manually. */ - nir_shader *nir = brw_blorp_build_nir_shader(brw, prog_key); + nir_shader *nir = brw_blorp_build_nir_shader(blorp, prog_key); struct brw_wm_prog_key wm_key; brw_blorp_init_wm_prog_key(&wm_key); wm_key.tex.compressed_multisample_layout_mask = @@ -1214,13 +1215,13 @@ brw_blorp_get_blit_kernel(struct brw_context *brw, wm_key.tex.msaa_16 = prog_key->tex_samples == 16; wm_key.multisample_fbo = prog_key->rt_samples > 1; - program = brw_blorp_compile_nir_shader(&brw->blorp, nir, &wm_key, false, + program = brw_blorp_compile_nir_shader(blorp, nir, &wm_key, false, &prog_data, &program_size); - brw->blorp.upload_shader(&brw->blorp, prog_key, sizeof(*prog_key), - program, program_size, - &prog_data, sizeof(prog_data), - ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); + blorp->upload_shader(blorp, prog_key, sizeof(*prog_key), + program, program_size, + &prog_data, sizeof(prog_data), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); } static void @@ -1274,7 +1275,7 @@ swizzle_to_scs(GLenum swizzle) } static void -surf_convert_to_single_slice(struct brw_context *brw, +surf_convert_to_single_slice(const struct isl_device *isl_dev, struct brw_blorp_surface_info *info) { /* This only makes sense for a single level and array slice */ @@ -1292,7 +1293,7 @@ surf_convert_to_single_slice(struct brw_context *brw, &x_offset_sa, &y_offset_sa); uint32_t byte_offset; - isl_tiling_get_intratile_offset_sa(&brw->isl_dev, info->surf.tiling, + isl_tiling_get_intratile_offset_sa(isl_dev, info->surf.tiling, info->view.format, info->surf.row_pitch, x_offset_sa, y_offset_sa, &byte_offset, @@ -1318,7 +1319,7 @@ surf_convert_to_single_slice(struct brw_context *brw, init_info.usage = info->surf.usage; init_info.tiling_flags = 1 << info->surf.tiling; - isl_surf_init_s(&brw->isl_dev, &info->surf, &init_info); + isl_surf_init_s(isl_dev, &info->surf, &init_info); assert(info->surf.row_pitch == init_info.min_pitch); /* The view is also different now. */ @@ -1329,13 +1330,13 @@ surf_convert_to_single_slice(struct brw_context *brw, } static void -surf_fake_interleaved_msaa(struct brw_context *brw, +surf_fake_interleaved_msaa(const struct isl_device *isl_dev, struct brw_blorp_surface_info *info) { assert(info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED); /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */ - surf_convert_to_single_slice(brw, info); + surf_convert_to_single_slice(isl_dev, info); info->surf.logical_level0_px = info->surf.phys_level0_sa; info->surf.samples = 1; @@ -1343,26 +1344,27 @@ surf_fake_interleaved_msaa(struct brw_context *brw, } static void -surf_retile_w_to_y(struct brw_context *brw, +surf_retile_w_to_y(const struct isl_device *isl_dev, struct brw_blorp_surface_info *info) { assert(info->surf.tiling == ISL_TILING_W); /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */ - surf_convert_to_single_slice(brw, info); + surf_convert_to_single_slice(isl_dev, info); /* On gen7+, we don't have interleaved multisampling for color render * targets so we have to fake it. * * TODO: Are we sure we don't also need to fake it on gen6? */ - if (brw->gen > 6 && info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { + if (isl_dev->info->gen > 6 && + info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { info->surf.logical_level0_px = info->surf.phys_level0_sa; info->surf.samples = 1; info->surf.msaa_layout = ISL_MSAA_LAYOUT_NONE; } - if (brw->gen == 6) { + if (isl_dev->info->gen == 6) { /* Gen6 stencil buffers have a very large alignment coming in from the * miptree. It's out-of-bounds for what the surface state can handle. * Since we have a single layer and level, it doesn't really matter as @@ -1385,7 +1387,7 @@ surf_retile_w_to_y(struct brw_context *brw, } void -brw_blorp_blit(struct brw_context *brw, +brw_blorp_blit(struct blorp_batch *batch, const struct brw_blorp_surf *src_surf, unsigned src_level, unsigned src_layer, enum isl_format src_format, int src_swizzle, @@ -1398,12 +1400,14 @@ brw_blorp_blit(struct brw_context *brw, float dst_x1, float dst_y1, GLenum filter, bool mirror_x, bool mirror_y) { + const struct brw_device_info *devinfo = batch->blorp->isl_dev->info; + struct brw_blorp_params params; brw_blorp_params_init(¶ms); - brw_blorp_surface_info_init(brw, ¶ms.src, src_surf, src_level, + brw_blorp_surface_info_init(batch->blorp, ¶ms.src, src_surf, src_level, src_layer, src_format, false); - brw_blorp_surface_info_init(brw, ¶ms.dst, dst_surf, dst_level, + brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, dst_surf, dst_level, dst_layer, dst_format, true); struct brw_blorp_blit_prog_key wm_prog_key; @@ -1486,7 +1490,7 @@ brw_blorp_blit(struct brw_context *brw, /* For some texture types, we need to pass the layer through the sampler. */ params.wm_inputs.src_z = params.src.z_offset; - if (brw->gen > 6 && + if (devinfo->gen > 6 && params.dst.surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) { assert(params.dst.surf.samples > 1); @@ -1531,7 +1535,7 @@ brw_blorp_blit(struct brw_context *brw, unreachable("Unrecognized sample count in brw_blorp_blit_params ctor"); } - surf_fake_interleaved_msaa(brw, ¶ms.dst); + surf_fake_interleaved_msaa(batch->blorp->isl_dev, ¶ms.dst); wm_prog_key.use_kill = true; } @@ -1590,7 +1594,7 @@ brw_blorp_blit(struct brw_context *brw, params.y1 = ALIGN(params.y1, y_align) / 2; /* Retile the surface to Y-tiled */ - surf_retile_w_to_y(brw, ¶ms.dst); + surf_retile_w_to_y(batch->blorp->isl_dev, ¶ms.dst); wm_prog_key.dst_tiled_w = true; wm_prog_key.use_kill = true; @@ -1606,7 +1610,7 @@ brw_blorp_blit(struct brw_context *brw, } } - if (brw->gen < 8 && params.src.surf.tiling == ISL_TILING_W) { + if (devinfo->gen < 8 && params.src.surf.tiling == ISL_TILING_W) { /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled. * Broadwell adds support for sampling from stencil. * @@ -1615,7 +1619,7 @@ brw_blorp_blit(struct brw_context *brw, * * TODO: what if this makes the texture size too large? */ - surf_retile_w_to_y(brw, ¶ms.src); + surf_retile_w_to_y(batch->blorp->isl_dev, ¶ms.src); wm_prog_key.src_tiled_w = true; } @@ -1641,15 +1645,12 @@ brw_blorp_blit(struct brw_context *brw, wm_prog_key.persample_msaa_dispatch = true; } - brw_blorp_get_blit_kernel(brw, ¶ms, &wm_prog_key); + brw_blorp_get_blit_kernel(batch->blorp, ¶ms, &wm_prog_key); for (unsigned i = 0; i < 4; i++) { params.src.view.channel_select[i] = swizzle_to_scs(GET_SWZ(src_swizzle, i)); } - struct blorp_batch batch; - blorp_batch_init(&brw->blorp, &batch, brw); - brw->blorp.exec(&batch, ¶ms); - blorp_batch_finish(&batch); + batch->blorp->exec(batch, ¶ms); } diff --git a/src/mesa/drivers/dri/i965/blorp_clear.c b/src/mesa/drivers/dri/i965/blorp_clear.c index 8bd2b5b52d2..0741bca3337 100644 --- a/src/mesa/drivers/dri/i965/blorp_clear.c +++ b/src/mesa/drivers/dri/i965/blorp_clear.c @@ -47,7 +47,7 @@ struct brw_blorp_const_color_prog_key }; static void -brw_blorp_params_get_clear_kernel(struct brw_context *brw, +brw_blorp_params_get_clear_kernel(struct blorp_context *blorp, struct brw_blorp_params *params, bool use_replicated_data) { @@ -55,8 +55,8 @@ brw_blorp_params_get_clear_kernel(struct brw_context *brw, memset(&blorp_key, 0, sizeof(blorp_key)); blorp_key.use_simd16_replicated_data = use_replicated_data; - if (brw->blorp.lookup_shader(&brw->blorp, &blorp_key, sizeof(blorp_key), - ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) + if (blorp->lookup_shader(blorp, &blorp_key, sizeof(blorp_key), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data)) return; void *mem_ctx = ralloc_context(NULL); @@ -83,19 +83,20 @@ brw_blorp_params_get_clear_kernel(struct brw_context *brw, struct brw_blorp_prog_data prog_data; unsigned program_size; const unsigned *program = - brw_blorp_compile_nir_shader(&brw->blorp, b.shader, &wm_key, use_replicated_data, + brw_blorp_compile_nir_shader(blorp, b.shader, &wm_key, use_replicated_data, &prog_data, &program_size); - brw->blorp.upload_shader(&brw->blorp, &blorp_key, sizeof(blorp_key), - program, program_size, - &prog_data, sizeof(prog_data), - ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); + blorp->upload_shader(blorp, &blorp_key, sizeof(blorp_key), + program, program_size, + &prog_data, sizeof(prog_data), + ¶ms->wm_prog_kernel, ¶ms->wm_prog_data); ralloc_free(mem_ctx); } void -blorp_fast_clear(struct brw_context *brw, const struct brw_blorp_surf *surf, +blorp_fast_clear(struct blorp_batch *batch, + const struct brw_blorp_surf *surf, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) { @@ -110,23 +111,21 @@ blorp_fast_clear(struct brw_context *brw, const struct brw_blorp_surf *surf, memset(¶ms.wm_inputs, 0xff, 4*sizeof(float)); params.fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE; - brw_get_fast_clear_rect(&brw->isl_dev, surf->aux_surf, + brw_get_fast_clear_rect(batch->blorp->isl_dev, surf->aux_surf, ¶ms.x0, ¶ms.y0, ¶ms.x1, ¶ms.y1); - brw_blorp_params_get_clear_kernel(brw, ¶ms, true); + brw_blorp_params_get_clear_kernel(batch->blorp, ¶ms, true); - brw_blorp_surface_info_init(brw, ¶ms.dst, surf, level, layer, + brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level, layer, surf->surf->format, true); - struct blorp_batch batch; - blorp_batch_init(&brw->blorp, &batch, brw); - brw->blorp.exec(&batch, ¶ms); - blorp_batch_finish(&batch); + batch->blorp->exec(batch, ¶ms); } void -blorp_clear(struct brw_context *brw, const struct brw_blorp_surf *surf, +blorp_clear(struct blorp_batch *batch, + const struct brw_blorp_surf *surf, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, enum isl_format format, union isl_color_value clear_color, @@ -162,28 +161,26 @@ blorp_clear(struct brw_context *brw, const struct brw_blorp_surf *surf, use_simd16_replicated_data = false; } - brw_blorp_params_get_clear_kernel(brw, ¶ms, use_simd16_replicated_data); + brw_blorp_params_get_clear_kernel(batch->blorp, ¶ms, + use_simd16_replicated_data); - brw_blorp_surface_info_init(brw, ¶ms.dst, surf, level, layer, + brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, level, layer, format, true); - struct blorp_batch batch; - blorp_batch_init(&brw->blorp, &batch, brw); - brw->blorp.exec(&batch, ¶ms); - blorp_batch_finish(&batch); + batch->blorp->exec(batch, ¶ms); } void -brw_blorp_ccs_resolve(struct brw_context *brw, struct brw_blorp_surf *surf, - enum isl_format format) +brw_blorp_ccs_resolve(struct blorp_batch *batch, + struct brw_blorp_surf *surf, enum isl_format format) { struct brw_blorp_params params; brw_blorp_params_init(¶ms); - brw_blorp_surface_info_init(brw, ¶ms.dst, surf, + brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf, 0 /* level */, 0 /* layer */, format, true); - brw_get_ccs_resolve_rect(&brw->isl_dev, ¶ms.dst.aux_surf, + brw_get_ccs_resolve_rect(batch->blorp->isl_dev, ¶ms.dst.aux_surf, ¶ms.x0, ¶ms.y0, ¶ms.x1, ¶ms.y1); @@ -198,10 +195,7 @@ brw_blorp_ccs_resolve(struct brw_context *brw, struct brw_blorp_surf *surf, * color" message. */ - brw_blorp_params_get_clear_kernel(brw, ¶ms, true); + brw_blorp_params_get_clear_kernel(batch->blorp, ¶ms, true); - struct blorp_batch batch; - blorp_batch_init(&brw->blorp, &batch, brw); - brw->blorp.exec(&batch, ¶ms); - blorp_batch_finish(&batch); + batch->blorp->exec(batch, ¶ms); } diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h b/src/mesa/drivers/dri/i965/blorp_priv.h index a28b5a7b73f..1f10f49c52a 100644 --- a/src/mesa/drivers/dri/i965/blorp_priv.h +++ b/src/mesa/drivers/dri/i965/blorp_priv.h @@ -62,7 +62,7 @@ struct brw_blorp_surface_info }; void -brw_blorp_surface_info_init(struct brw_context *brw, +brw_blorp_surface_info_init(struct blorp_context *blorp, struct brw_blorp_surface_info *info, const struct brw_blorp_surf *surf, unsigned int level, unsigned int layer, diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e509417e621..e59c26e7883 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -332,13 +332,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw, brw_blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true, &dst_level, &tmp_surfs[2]); - brw_blorp_blit(brw, &src_surf, src_level, src_layer, + struct blorp_batch batch; + blorp_batch_init(&brw->blorp, &batch, brw); + brw_blorp_blit(&batch, &src_surf, src_level, src_layer, brw_blorp_to_isl_format(brw, src_format, false), src_swizzle, &dst_surf, dst_level, dst_layer, brw_blorp_to_isl_format(brw, dst_format, true), src_x0, src_y0, src_x1, src_y1, dst_x0, dst_y0, dst_x1, dst_y1, filter, mirror_x, mirror_y); + blorp_batch_finish(&batch); intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer); @@ -728,7 +731,10 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, DBG("%s (fast) to mt %p level %d layer %d\n", __FUNCTION__, irb->mt, irb->mt_level, irb->mt_layer); - blorp_fast_clear(brw, &surf, level, layer, x0, y0, x1, y1); + struct blorp_batch batch; + blorp_batch_init(&brw->blorp, &batch, brw); + blorp_fast_clear(&batch, &surf, level, layer, x0, y0, x1, y1); + blorp_batch_finish(&batch); /* Now that the fast clear has occurred, put the buffer in * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing @@ -742,9 +748,12 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, union isl_color_value clear_color; memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4); - blorp_clear(brw, &surf, level, layer, x0, y0, x1, y1, + struct blorp_batch batch; + blorp_batch_init(&brw->blorp, &batch, brw); + blorp_clear(&batch, &surf, level, layer, x0, y0, x1, y1, (enum isl_format)brw->render_target_format[format], clear_color, color_write_disable); + blorp_batch_finish(&batch); if (intel_miptree_is_lossless_compressed(brw, irb->mt)) { /* Compressed buffers can be cleared also using normal rep-clear. In @@ -819,7 +828,11 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt) unsigned level = 0; brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp); - brw_blorp_ccs_resolve(brw, &surf, brw_blorp_to_isl_format(brw, format, true)); + struct blorp_batch batch; + blorp_batch_init(&brw->blorp, &batch, brw); + brw_blorp_ccs_resolve(&batch, &surf, + brw_blorp_to_isl_format(brw, format, true)); + blorp_batch_finish(&batch); mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; } @@ -837,7 +850,10 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, struct brw_blorp_surf surf; brw_blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp); - blorp_gen6_hiz_op(brw, &surf, level, layer, op); + struct blorp_batch batch; + blorp_batch_init(&brw->blorp, &batch, brw); + blorp_gen6_hiz_op(&batch, &surf, level, layer, op); + blorp_batch_finish(&batch); } /**