From: bunnie <bunnie@kosagi.com>
Date: Wed, 1 Jan 2020 10:49:00 +0000 (+0800)
Subject: add the possibility for a "precise" clock solution
X-Git-Tag: 24jan2021_ls180~772^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=219bb7f294c14dde5072ac3282cc33943931a64c;p=litex.git

add the possibility for a "precise" clock solution

If clocks and multipliers are planned well, we can have
a zero-error solution for clocks. Suggest to change < to <= in
margin comparison loop, so that a "perfect" solution is allowed
to converge.
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 5d3ce6ec..03b7e426 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -74,7 +74,7 @@ class XilinxClocking(Module, AutoCSR):
                         valid = False
                         for d in range(*self.clkout_divide_range):
                             clk_freq = vco_freq/d
-                            if abs(clk_freq - f) < f*m:
+                            if abs(clk_freq - f) <= f*m:
                                 config["clkout{}_freq".format(n)]   = clk_freq
                                 config["clkout{}_divide".format(n)] = d
                                 config["clkout{}_phase".format(n)]  = p