From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 13:07:21 +0000 (+0100)
Subject: add class containing all regfiles
X-Git-Tag: div_pipeline~636^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21a1e0b121a740cc4da8b6b6e64bde2b154925da;p=soc.git

add class containing all regfiles
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index d44242a5..dc92f0c4 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -126,3 +126,13 @@ class SPRRegs(RegFile):
         super().__init__(64, n_sprs)
         self.w_ports = [self.write_port("dest")]
         self.r_ports = [self.read_port("src")]
+
+
+class RegFiles:
+    def __init__(self):
+        self.int = IntRegs()
+        self.cr = CRRegs()
+        self.xer = XERRegs()
+        self.fasr = FastRegs()
+        self.spr = SPRRegs()
+