From: Luke Kenneth Casson Leighton Date: Sat, 30 May 2020 10:58:30 +0000 (+0100) Subject: still experimenting with ALU-CompUnit interaction X-Git-Tag: div_pipeline~737 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21a4055aa3277d4ad4970bac8ec679c22b93f6d1;p=soc.git still experimenting with ALU-CompUnit interaction --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 3523e3fb..a87fa486 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -199,7 +199,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # read-done,wr-proceed latch m.d.comb += rok_l.s.eq(self.issue_i) # set up when issue starts - m.d.comb += rok_l.r.eq(self.alu.p.ready_o) # off when ALU acknowledges + m.d.comb += rok_l.r.eq(self.alu.n.valid_o) # off when ALU acknowledges # wr-done, back-to-start latch m.d.comb += rst_l.s.eq(all_rd) # set when read-phase is fully done @@ -293,7 +293,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # ALU says "valid". m.submodules.alu_l = alu_l = SRLatch(False, name="alu") m.d.comb += self.alu.n.ready_i.eq(alu_l.qn) - m.d.sync += alu_l.r.eq(self.alu.n.valid_o) # valid for one extra + m.d.sync += alu_l.r.eq(self.alu.n.valid_o & alu_l.q) m.d.comb += alu_l.s.eq(all_rd_pulse) # output the data from the latch on go_write