From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 8 Jul 2019 20:58:07 +0000 (+0200)
Subject: soc_core: declare csr address size when registering csr, fixes #212
X-Git-Tag: 24jan2021_ls180~1115
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21a5aaa4a62d31568de992e650fd9daa2899b8db;p=litex.git

soc_core: declare csr address size when registering csr, fixes #212
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 7297111b..0e0a3017 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -298,7 +298,7 @@ class SoCCore(Module):
         self.add_csr_master(self.wishbone2csr.csr)
         self.config["CSR_DATA_WIDTH"] = csr_data_width
         self.config["CSR_ALIGNMENT"] = csr_alignment
-        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone)
+        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
 
         # Add UART
         if with_uart: