From: lkcl <lkcl@web>
Date: Sat, 9 Jan 2021 16:46:31 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~520
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21c70fac9abedf3d1dc3dfe2ed60ad0d75fc8ba8;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 5f0e8d176..c84817cba 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -257,12 +257,6 @@ and other modes have all been removed, for clarity and simplicity:
         i++;
         j++;
 
-When RA is marked as Vectorised the mode switches to an anomalous
-version similar to Indexed.  The element indices increment to select a
-64 bit base address, effectively as if the src elwidth was hard-set to
-"default".  The important thing to note is that `i*op_width` is *not*
-added on to the base address unless RA is marked as a scalar address.
-
 # Remapped LD/ST
 
 In the [[sv/propagation]] page the concept of "Remapping" is described.