From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 09:53:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1727
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21cd43b7221ec4e00d4e7e3a8fb3b44b6456756a;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 7d1662b72..3370879d3 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -28,7 +28,8 @@ that same Scalar instruction is Prefixed*.
 Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
-  to/from SVSRR1. Register Files as Standard Power ISA.
+  to/from SVSRR1. Register Files as Standard Power ISA. `scalar identity`
+  implemented.
 * **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
@@ -53,6 +54,12 @@ is permitted to implement the DCT REMAP capability, but will not be
 permitted to declare meeting the 3D/Advanced Level unless implementing
 *all* REMAP Capabilities.
 
+**Power ISA Compliancy Levels**
+
+The SV Compliancy Levels have nothing to do with the Power ISA Compliancy
+Levels (SFS, SFFS, Linux, AIX). They are separate and independent. It
+is perfectly fine to implement Ultra-Embedded on AIX, and perfectly fine to implement 3D/Advanced on SFS. **Compliance with SV Levels does not convey or remove the obligation of Compliance with SFS/SFFS/Linux/AIX Levels and vice-versa**.
+
 # Ultra-Embedded Level
 
 This level exists as an entry-level into SVP64, most suited to resource
@@ -60,7 +67,8 @@ constrained soft cores, or Hardware implementations where unit cost is a much
 higher priority than execution speed.
 
 This level sets the bare minimum requirements, where everything with the
-exception of the `setvl` instruction may be software-emulated through
+exception of `scalar identity` and
+the `setvl` instruction may be software-emulated through
 JIT Translation or Illegal Instruction traps.  SVSTATE, as effectively
 a Sub-Program-Counter, joins MSR and PC (CIA, NIA)
 as direct peers and must be switched on any context-switch (Trap or
@@ -80,11 +88,17 @@ Illegal Instruction Trap **must** be raised on:
 * Any SV instructions not implemented
 * any unimplemented SV Context SPRs read or written 
 * all unimplemented uses of the SVP64 Prefix
+* non-scalar-identity SVP64 instructions
 
 Implementors are free and clear to implement any other features of
 SVP64 however only by meeting all of the mandatory requirements above
 will Compliance with the Ultra-Embedded Level be achieved.
 
+Note that `scalar identity` is defined as being when the execution of
+an SVP64 Prefixed instruction is identical in every respect to
+Scalar non-prefixed, i.e. as if the Prefix had not been present.
+Additionally all SV SPRs must be zero and the 24-bit `RM` field must be zero.
+
 # Embedded Level
 
 This level is more suitable for Hardware implementations where performance and power saving begins to matter.  A second instruction, `svstep`, used