From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Aug 2018 08:52:15 +0000 (+0100)
Subject: add memory map configs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21ea39d7cdae5bba0c3e3f81d849a885a676500e;p=pinmux.git

add memory map configs
---

diff --git a/src/ifacebase.py b/src/ifacebase.py
index e4a80ec..86d7030 100644
--- a/src/ifacebase.py
+++ b/src/ifacebase.py
@@ -69,6 +69,7 @@ class InterfacesBase(UserDict):
                 ln = ln.split("\t")
                 name = ln[0]  # will have uart
                 count = int(ln[1])  # will have count of uart
+
                 # spec looks like this:
                 """
                 [{'name': 'sda', 'outen': True},
@@ -91,7 +92,21 @@ class InterfacesBase(UserDict):
                 else:
                     iface = ikls(name, spec, ganged, count == 1)
                     self.ifaceadd(name, count, iface)
+                cfgs = self.getconfigs(name, count)
+                iface.configs = cfgs
+                print name, count, cfgs
+        exit(0)
 
+    def getconfigs(self, fname, count):
+        cfgs = []
+        for i in range(count):
+            if count == 1:
+                name = fname
+            else:
+                name = "%s%d" % (fname, i)
+            cfgs.append(self.configs.get(name, {}))
+        return cfgs
+            
     def getifacetype(self, fname):
         # finds the interface type, e.g sd_d0 returns "inout"
         for iface in self.values():
diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index cee50e1..e33c1fa 100644
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -61,10 +61,15 @@ def pinspec():
                       }
 
     ps = PinSpec(pinbanks, fixedpins, function_names,
-                 {'lcd': {'bus': 'fastbus'},
+                 {'lcd': {'bus': 'fastbus',
+                          'mmap': [['Cfg', 0x20000, 10]
+                                  ]},
                   'jtag': {'bus': 'fastbus'},
                   'fb': {'bus': 'fastbus'},
-                  'sdr': {'bus': 'fastbus'}
+                  'sdr': {'bus': 'fastbus',
+                          'mmap': [['Mem', 0x50000000, 0x400000],
+                                   ['Cfg', 0x21000, 12]
+                                  ]},
                  })
 
     # Bank A, 0-27