From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Thu, 17 Oct 2013 15:20:45 +0000 (-0500)
Subject: config: Fix memtest example script
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21f1e1676316eb162d94545c49ee6835fc7ce7e5;p=gem5.git

config: Fix memtest example script
---

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 65f3ec315..13385b61f 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -83,6 +83,10 @@ parser.add_option("--progress", type="int", default=1000,
                   metavar="NLOADS",
                   help="Progress message interval "
                   "[default: %default]")
+parser.add_option("--sys-clock", action="store", type="string",
+                  default='1GHz',
+                  help = """Top-level clock for blocks running at system
+                  speed""")
 
 (options, args) = parser.parse_args()
 
@@ -110,7 +114,7 @@ if len(treespec) < 1:
 
 # define prototype L1 cache
 proto_l1 = BaseCache(size = '32kB', assoc = 4,
-                     hit_latency = '1ns', response_latency = '1ns',
+                     hit_latency = 1, response_latency = 1,
                      tgts_per_mshr = 8)
 
 if options.blocking:
@@ -145,7 +149,12 @@ system = System(funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(latency = "100ns"),
                 cache_line_size = block_size)
-system.clk_domain = SrcClockDomain(clock =  options.sys_clock)
+
+
+system.voltage_domain = VoltageDomain(voltage = '1V')
+
+system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
+                        voltage_domain = system.voltage_domain)
 
 def make_level(spec, prototypes, attach_obj, attach_port):
      fanout = spec[0]