From: Luke Kenneth Casson Leighton Date: Tue, 3 Nov 2020 13:29:07 +0000 (+0000) Subject: add VERSA-ECP5 images, rename FPGA page X-Git-Tag: convert-csv-opcode-to-binary~1887 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21f6eeb945ba2e913723832bafb6f7dbf18b7bab;p=libreriscv.git add VERSA-ECP5 images, rename FPGA page --- diff --git a/HDL_workflow/2020-11-03_13-22.png b/HDL_workflow/2020-11-03_13-22.png new file mode 100644 index 000000000..1eb99708e Binary files /dev/null and b/HDL_workflow/2020-11-03_13-22.png differ diff --git a/HDL_workflow/2020-11-03_13-25.png b/HDL_workflow/2020-11-03_13-25.png new file mode 100644 index 000000000..875baa4d5 Binary files /dev/null and b/HDL_workflow/2020-11-03_13-25.png differ diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn new file mode 100644 index 000000000..5ff231436 --- /dev/null +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -0,0 +1,165 @@ +# ULX3S JTAG Connection with STLINKV2 + +Cross referenced with: + + + + + +## Original Instructions + +lkcl: + + +> the JTAG TAP interface on the *FPGA* is hard-coded silicon. + +> the JTAG TAP interface connected on the processor and soft-implemented +> *by* the FPGA is likely completely inaccessible until someone +> allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config. +> +> which means: someone's going to have to to through this file: +> +> (which defines the pin allocations) +> +> and in this file do some Voodoo Magic on this file's TestSoC: +> +> +> similar to these four lines: +> +> +> but instead doing something like... err.... +> +> gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2 +> +> self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n" +> +> self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc. +> +> and then request gpio1 for the other 2 pins +> +> theeeen you'll need to go back to that ulx3s.py litex platform file, +> look up the pin names B11, C11, A10, A11, and find out what the hell +> they are, whether they're suitable for use. +> +> if they are, then great! these are what you wire up the STLINKv2 to, +> according to what you decided to connect to just above. +> +> but for god's sake do not get this wrong, such as driving an input as +> an output or vice-versa, or wiring up 5.0V to GND with those +> jumper-cables. +> +> do *NOT* randomly upload and power up the ulx3s until this has been +> THOROUGHLY triple-checked. or, you are entirely free to not bother +> and to end up learning the hard way by destroying the FPGA. + +## Connecting the dots: + +Accurate render of board for reference + +STLINKV2 Pins and JTAG signals schematic/user guide + +Litex platform file + + ("gpio", 0, + Subsignal"p", Pins("B11")), + Subsignal("n", Pins("C11")), + IOStandard("LVCMOS33") + ), + ("gpio", 1, + Subsignal("p", Pins("A10")), + Subsignal("n", Pins("A11")), + IOStandard("LVCMOS33") + ), + +ULX3S FPGA constraints file + + LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK + LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK + LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK + LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK + +ULX3S FPGA Schematic + +``` +J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header. +For MALE VERTICAL header, SWAP EVEN and ODD pin numbers. + + J1 + + Label [GP{x}]|PCB pin label|[GN{x}] Label + (Pin count +)(Pin count -) +_________________V__________V________________ + IO VOLT REF 3V3 2 |3.3V| 1 NOT CONNECTED + [GND] 4 | -| | 3 NOT CONNECTED +PCLKT0_0 [GP0] 6 | 0 | 5 [GN0] PCLKC0_0 +PCLKT0_1 [GP1] 8 | 1 | 7 [GN1] PCLKC0_1 + + +GP,GN 0-7 single-ended connected to Bank0 +GP,GN 8-13 differential bidirectional connected to BANK7 +``` + +Connecting all the dots: + +``` +Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label | + 5 (J1_5-) | 0 | C11 | gn[0] | PCLKC0_0 | + 6 (J1_5+) | 0 | B11 | gp[0] | PCLKT0_0 | + 7 (J1_7-) | 1 | A11 | gn[1] | PCLKC0_1 | + 8 (J1_7+) | 1 | A10 | gp[1] | PCLKT0_1 | +``` + +As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs. + +Proposed FPGA External Pin to STLINK JTAG pin connections: + +``` + all pin #'s have headers pins on the fpga unless denoted as (no header) + ______________________________________________________________________________ +| | board | | | | | +| | label | | |STLINKV2 JTAG | | +| pin # | # | FPGA IO PAD |GPIO # (n/p) | Pin # (Signal)|Wire Colour| +|_____________|_______|_____________|_____________|________________|___________| +|1 (no header)| 3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT | +|2 | 3.3v | IO VOLT REF | IO VOLT REF | 2 (MCU VDD) | Red | +|3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT | +|4 |-|(GND)| NONE | GND | 4 (GND) | Black | +|5 (J1_5-) | 0 | C11 | gn[0] | 5 (JTDI) | Green | +|6 (J1_5+) | 0 | B11 | gp[0] | 7 (JTMS) | Blue | +|7 (J1_7-) | 1 | A11 | gn[1] | 9 (JTCK) | White | +|8 (J1_7+) | 1 | A10 | gp[1] | 13 (JTDO) | Yellow | +|_____________|_______|_____________|_____________|________________|___________| +``` + +Complete diagram: + +``` +Pins intentionally have no header or are not connected to the STLINKVT are marked +and therefore have no value are marked with 'NOT' + +(ST# JTAG) = (STLINKV2 pin # JTAG signal name) + + + J1 + Wire Wire + Colour [GP{x}]|PCB label|[GN{x}] Colour +(ST# JTAG) (Pin count +)(Pin count -) (ST# JTAG) + ________________________V__________V_________________________ +| | +|( 2 JVDD) red [VREF] 2 |3.3V| 1 NOT NOT NOT | +|( 4 JGND) black [GND] 4 | -| | 3 NOT NOT NOT | +|( 7 JTMS) blue [GP0] 6 | 0 | 5 [GN0] green (5 JTDI) | +|(13 JTDO) yellow [GP1] 8 | 1 | 7 [GN1] white (9 JTCK) | +|_____________________________________________________________| +``` + +## Images of wires on FPGA and on STLINKV2 + +[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]] + +## Questions + +Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG? + +Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us? + diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn deleted file mode 100644 index 5ff231436..000000000 --- a/HDL_workflow/fpga.mdwn +++ /dev/null @@ -1,165 +0,0 @@ -# ULX3S JTAG Connection with STLINKV2 - -Cross referenced with: - - - - - -## Original Instructions - -lkcl: - - -> the JTAG TAP interface on the *FPGA* is hard-coded silicon. - -> the JTAG TAP interface connected on the processor and soft-implemented -> *by* the FPGA is likely completely inaccessible until someone -> allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config. -> -> which means: someone's going to have to to through this file: -> -> (which defines the pin allocations) -> -> and in this file do some Voodoo Magic on this file's TestSoC: -> -> -> similar to these four lines: -> -> -> but instead doing something like... err.... -> -> gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2 -> -> self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n" -> -> self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc. -> -> and then request gpio1 for the other 2 pins -> -> theeeen you'll need to go back to that ulx3s.py litex platform file, -> look up the pin names B11, C11, A10, A11, and find out what the hell -> they are, whether they're suitable for use. -> -> if they are, then great! these are what you wire up the STLINKv2 to, -> according to what you decided to connect to just above. -> -> but for god's sake do not get this wrong, such as driving an input as -> an output or vice-versa, or wiring up 5.0V to GND with those -> jumper-cables. -> -> do *NOT* randomly upload and power up the ulx3s until this has been -> THOROUGHLY triple-checked. or, you are entirely free to not bother -> and to end up learning the hard way by destroying the FPGA. - -## Connecting the dots: - -Accurate render of board for reference - -STLINKV2 Pins and JTAG signals schematic/user guide - -Litex platform file - - ("gpio", 0, - Subsignal"p", Pins("B11")), - Subsignal("n", Pins("C11")), - IOStandard("LVCMOS33") - ), - ("gpio", 1, - Subsignal("p", Pins("A10")), - Subsignal("n", Pins("A11")), - IOStandard("LVCMOS33") - ), - -ULX3S FPGA constraints file - - LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK - LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK - LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK - LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK - -ULX3S FPGA Schematic - -``` -J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header. -For MALE VERTICAL header, SWAP EVEN and ODD pin numbers. - - J1 - - Label [GP{x}]|PCB pin label|[GN{x}] Label - (Pin count +)(Pin count -) -_________________V__________V________________ - IO VOLT REF 3V3 2 |3.3V| 1 NOT CONNECTED - [GND] 4 | -| | 3 NOT CONNECTED -PCLKT0_0 [GP0] 6 | 0 | 5 [GN0] PCLKC0_0 -PCLKT0_1 [GP1] 8 | 1 | 7 [GN1] PCLKC0_1 - - -GP,GN 0-7 single-ended connected to Bank0 -GP,GN 8-13 differential bidirectional connected to BANK7 -``` - -Connecting all the dots: - -``` -Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label | - 5 (J1_5-) | 0 | C11 | gn[0] | PCLKC0_0 | - 6 (J1_5+) | 0 | B11 | gp[0] | PCLKT0_0 | - 7 (J1_7-) | 1 | A11 | gn[1] | PCLKC0_1 | - 8 (J1_7+) | 1 | A10 | gp[1] | PCLKT0_1 | -``` - -As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs. - -Proposed FPGA External Pin to STLINK JTAG pin connections: - -``` - all pin #'s have headers pins on the fpga unless denoted as (no header) - ______________________________________________________________________________ -| | board | | | | | -| | label | | |STLINKV2 JTAG | | -| pin # | # | FPGA IO PAD |GPIO # (n/p) | Pin # (Signal)|Wire Colour| -|_____________|_______|_____________|_____________|________________|___________| -|1 (no header)| 3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT | -|2 | 3.3v | IO VOLT REF | IO VOLT REF | 2 (MCU VDD) | Red | -|3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT | -|4 |-|(GND)| NONE | GND | 4 (GND) | Black | -|5 (J1_5-) | 0 | C11 | gn[0] | 5 (JTDI) | Green | -|6 (J1_5+) | 0 | B11 | gp[0] | 7 (JTMS) | Blue | -|7 (J1_7-) | 1 | A11 | gn[1] | 9 (JTCK) | White | -|8 (J1_7+) | 1 | A10 | gp[1] | 13 (JTDO) | Yellow | -|_____________|_______|_____________|_____________|________________|___________| -``` - -Complete diagram: - -``` -Pins intentionally have no header or are not connected to the STLINKVT are marked -and therefore have no value are marked with 'NOT' - -(ST# JTAG) = (STLINKV2 pin # JTAG signal name) - - - J1 - Wire Wire - Colour [GP{x}]|PCB label|[GN{x}] Colour -(ST# JTAG) (Pin count +)(Pin count -) (ST# JTAG) - ________________________V__________V_________________________ -| | -|( 2 JVDD) red [VREF] 2 |3.3V| 1 NOT NOT NOT | -|( 4 JGND) black [GND] 4 | -| | 3 NOT NOT NOT | -|( 7 JTMS) blue [GP0] 6 | 0 | 5 [GN0] green (5 JTDI) | -|(13 JTDO) yellow [GP1] 8 | 1 | 7 [GN1] white (9 JTCK) | -|_____________________________________________________________| -``` - -## Images of wires on FPGA and on STLINKV2 - -[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]] - -## Questions - -Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG? - -Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us? -