From: Catherine <whitequark@whitequark.org>
Date: Sat, 11 Dec 2021 16:24:47 +0000 (+0000)
Subject: Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values
X-Git-Tag: yosys-0.13~37
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=21fbdb6638bc00758dfe7aaac93c5805160168d5;p=yosys.git

Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values

write_verilog: dump zero width sigspecs correctly
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21fbdb6638bc00758dfe7aaac93c5805160168d5