From: Clifford Wolf Date: Fri, 29 Mar 2019 23:09:42 +0000 (+0100) Subject: Merge pull request #907 from YosysHQ/clifford/fix906 X-Git-Tag: yosys-0.9~211 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22035c20ff071ec5c30990258850ecf97de5d5b3;p=yosys.git Merge pull request #907 from YosysHQ/clifford/fix906 Build Verilog parser with -DYYMAXDEPTH=100000 --- 22035c20ff071ec5c30990258850ecf97de5d5b3