From: lkcl <lkcl@web>
Date: Fri, 17 Sep 2021 22:43:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=220a90fc6d9ec42360619b0cf9f91b58123db0a7;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index d3d7f4a41..660722b39 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -316,6 +316,9 @@ considered, exactly as is the case in Scalar Power ISA v3.0B
 only time in the entirety of SVP64 that has side-effects when
 a predicate mask bit is clear.  **All** other SVP64 operations
 entirely skip an element when sz=0 and a predicate mask bit is zero.
+It is also critical to emphasise that in this unusual mode, 
+no other side-effects occur: **only** CTR is decremented, i.e. the
+rest of the Branch operation iss skipped.
 
 # VLSET Mode