From: lkcl <lkcl@web>
Date: Wed, 30 Dec 2020 17:30:10 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~698
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=220af31650ae9f7341a2933e68030d0989bd6ace;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 2fbb61f98..c89d0995b 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -283,7 +283,12 @@ let alone Vectors of 8 bit.
 The solution comes in terms of rethinking the definition of a Register
 File.  The typical regfile may be considered to be a multi-ported SRAM
 block, 64 bits wide and usually 32 entries deep, to give 32 64 bit
-registers.  Conceptually, to get our variable element width vectors,
+registers.  In c this would be:
+
+    typedef uint64_t reg_t;
+    reg_t int_regfile[32]; // standard scalar 32x 64bit
+
+Conceptually, to get our variable element width vectors,
 we may think of the regfile as instead being the following c-based data
 structure: