From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 2 Jun 2019 17:10:44 +0000 (+0200)
Subject: boards/platform/arty: add Arty A7-100 variant
X-Git-Tag: 24jan2021_ls180~1190
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=220e2bdc6e8e68244c53c685282a318e48dfef82;p=litex.git

boards/platform/arty: add Arty A7-100 variant
---

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index aa38cf0a..36d64a3f 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -239,8 +239,12 @@ class Platform(XilinxPlatform):
     default_clk_name = "clk100"
     default_clk_period = 10.0
 
-    def __init__(self):
-        XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain="vivado")
+    def __init__(self, variant="a7-35"):
+        device = {
+            "a7-35":  "xc7a35ticsg324-1L",
+            "a7-100": "xc7a100tcsg324-1"
+        }[variant]
+        XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
         self.toolchain.additional_commands = \