From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 10 Jul 2019 14:51:08 +0000 (+0200)
Subject: soc_zynq: add missing axi hp0 clock
X-Git-Tag: 24jan2021_ls180~1110
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=220f43753ba13554cddea984c7a0f8a6e9e21424;p=litex.git

soc_zynq: add missing axi hp0 clock
---

diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index 0c237a65..f8b1784f 100644
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -138,6 +138,9 @@ class SoCZynq(SoCCore):
         self.axi_hp0 = axi_hp0 = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
         self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
         self.ps7_params.update(
+            # axi hp0 clk
+            i_M_AXI_HP0_ACLK=ClockSignal("sys"),
+
             # axi hp0 aw
             i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,
             o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,