From: lkcl <lkcl@web>
Date: Mon, 6 Sep 2021 15:52:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~205
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=221ff21a8683aaf70463c57500b38bb3792b788c;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index b2a500a02..fa1b8c893 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -146,8 +146,9 @@ Indexed LD is:
         ireg[RT+j] <= MEM[EA];
         if (!RT.isvec)
             break # destination scalar, end immediately
-        if (!RA.isvec && !RB.isvec)
-            break # scalar-scalar
+        if svctx.ldstmode != elementstride:
+            if (!RA.isvec && !RB.isvec)
+                break # scalar-scalar
         if (RA.isvec) i++;
         if (RAupdate.isvec) u++;
         if (RB.isvec) k++;