From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 29 Sep 2022 11:18:03 +0000 (+0100)
Subject: add bigint examples
X-Git-Tag: opf_rfc_ls005_v1~268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2230fb3e847291457556738cb6d0867540cbe977;p=libreriscv.git

add bigint examples
---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 2a12c911d..c70a7877a 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1232,13 +1232,46 @@ operations.
   76                        svshape 7, 0, 0, 7, 0
   77                        svremap 31, 1, 0, 0, 0, 0, 0 # different order
   78                        sv.subf *0, *8, *16
-  79
-  80                 REMAP sv.subf RT,RA,RB - inverted application of RA/RB
-  81                                          left/right due to subf
 ```
 
 <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py;hb=HEAD>
 
+## Big-Integer Math
+
+Remarkably, `sv.addeo` is inherently a big-integer Vector Add, using `CA`
+chaining between **Scalar** operations.
+Using Vector LD/ST and recalling that the first and last `CA` may
+be chained in and out of an entire **Vector**, unlimited-length arithmetic is
+possible.
+
+```
+  26     # test_sv_bigint_add
+  32
+  33         r3/r2: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff +
+  34         r5/r4: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 =
+  35         r1/r0: 0x8000_0000_0000_0002 0x0000_0000_0000_0000
+  36
+  37                          sv.addeo *0, *2, *4
+```
+
+A 128/64-bit shift may be used as a Vector shift by a Scalar amount, by merging
+two 64-bit consecutive registers in succession.
+
+```
+  62     # test_sv_bigint_scalar_shiftright(self):
+  64
+  65     r3                    r2                    r1                       r4
+  66     0x0000_0000_0000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4
+  67     0x0000_0000_0000_0002 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
+  68
+  69                          sv.dsrd *0,*1,4,1
+```
+
+Additional 128/64 Mul and Div/Mod instructions may similarly be exploited
+to perform roll-over in arbitrary-length arithmetic.
+
+<https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_bigint.py;hb=HEAD>
+
 [[!tag opf_rfc]]
 
 [^zolc]: first introduced in DSPs, Zero-Overhead Loops are astoundingly effective in reducing total number of instructions executed or needed. [ZOLC](https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.301.4646&rep=rep1&type=pdf) reduces instructions by **25 to 80 percent**.