From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 17 Feb 2020 10:45:43 +0000 (+0000)
Subject: cpu: Fix vector renaming bug
X-Git-Tag: v20.0.0.0~474
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2235168b72537535d74c645a70a85479801e0651;p=gem5.git

cpu: Fix vector renaming bug

The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/25009

moved initialization of vecMode out of initializing list.
In this way regFile gets initialized with an invalid initial renaming
mode.

Change-Id: Ib7bab9eaac0f5850fd3b3151584132f809a641e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25430
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e29dcf0ca..e2c727008 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -99,6 +99,9 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       iew(this, params),
       commit(this, params),
 
+      /* It is mandatory that all SMT threads use the same renaming mode as
+       * they are sharing registers and rename */
+      vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])),
       regFile(params->numPhysIntRegs,
               params->numPhysFloatRegs,
               params->numPhysVecRegs,
@@ -128,12 +131,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
       system(params->system),
       lastRunningCycle(curCycle())
 {
-    auto *the_isa = dynamic_cast<TheISA::ISA *>(params->isa[0]);
-    assert(the_isa);
-    /* It is mandatory that all SMT threads use the same renaming mode as
-     * they are sharing registers and rename */
-    vecMode = RenameMode<TheISA::ISA>::init(the_isa);
-
     if (!params->switched_out) {
         _status = Running;
     } else {