From: Daniel R. Carvalho Date: Tue, 3 Sep 2019 13:24:23 +0000 (+0200) Subject: configs: Port MemConfig to the common object list X-Git-Tag: v19.0.0.0~496 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=224da08be767b51e8148e5f3e6e0da2e2ea77add;p=gem5.git configs: Port MemConfig to the common object list Port MemConfig to use the common object list. Change-Id: If421c2745ac3431718a5170314045b456fc64a90 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592 Tested-by: kokoro Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg --- diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 3910cacbd..7f737761e 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -40,59 +40,9 @@ from __future__ import print_function from __future__ import absolute_import import m5.objects -import inspect -import sys -from textwrap import TextWrapper +from common import ObjectList from . import HMC -# Dictionary of mapping names of real memory controller models to -# classes. -_mem_classes = {} - -def is_mem_class(cls): - """Determine if a class is a memory controller that can be instantiated""" - - # We can't use the normal inspect.isclass because the ParamFactory - # and ProxyFactory classes have a tendency to confuse it. - try: - return issubclass(cls, m5.objects.AbstractMemory) and \ - not cls.abstract - except TypeError: - return False - -def get(name): - """Get a memory class from a user provided class name.""" - - try: - mem_class = _mem_classes[name] - return mem_class - except KeyError: - print("%s is not a valid memory controller." % (name,)) - sys.exit(1) - -def print_mem_list(): - """Print a list of available memory classes.""" - - print("Available memory classes:") - doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t") - for name, cls in _mem_classes.items(): - print("\t%s" % name) - - # Try to extract the class documentation from the class help - # string. - doc = inspect.getdoc(cls) - if doc: - for line in doc_wrapper.wrap(doc): - print(line) - -def mem_names(): - """Return a list of valid memory names.""" - return list(_mem_classes.keys()) - -# Add all memory controllers in the object hierarchy. -for name, cls in inspect.getmembers(m5.objects, is_mem_class): - _mem_classes[name] = cls - def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size): """ Helper function for creating a single memoy controller from the given @@ -200,7 +150,7 @@ def config_mem(options, system): if 2 ** intlv_bits != nbr_mem_ctrls: fatal("Number of memory channels must be a power of 2") - cls = get(opt_mem_type) + cls = ObjectList.mem_list.get(opt_mem_type) mem_ctrls = [] if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory): diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py index a8b2fcc21..62e0db10f 100644 --- a/configs/common/ObjectList.py +++ b/configs/common/ObjectList.py @@ -139,6 +139,7 @@ bp_list = ObjectList(m5.objects.BranchPredictor) cpu_list = CPUList(m5.objects.BaseCPU) hwp_list = ObjectList(m5.objects.BasePrefetcher) indirect_bp_list = ObjectList(m5.objects.IndirectPredictor) +mem_list = ObjectList(m5.objects.AbstractMemory) def _subclass_tester(name): sub_class = getattr(m5.objects, name, None) diff --git a/configs/common/Options.py b/configs/common/Options.py index 6afdc5a8a..a1cbf4e70 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -47,7 +47,6 @@ from m5.objects import * from .Benchmarks import * from . import ObjectList -from . import MemConfig from . import PlatformConfig def _listCpuTypes(option, opt, value, parser): @@ -67,7 +66,7 @@ def _listIndirectBPTypes(option, opt, value, parser): sys.exit(0) def _listMemTypes(option, opt, value, parser): - MemConfig.print_mem_list() + ObjectList.mem_list.print() sys.exit(0) def _listPlatformTypes(option, opt, value, parser): @@ -93,7 +92,7 @@ def addNoISAOptions(parser): action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help = "number of memory channels") diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index ceba1474a..23fe630a5 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -48,7 +48,6 @@ from os.path import join as joinpath from common import CpuConfig from . import ObjectList -from . import MemConfig import m5 from m5.defines import buildEnv @@ -97,7 +96,7 @@ def setCPUClass(options): def setMemClass(options): """Returns a memory controller class.""" - return MemConfig.get(options.mem_type) + return ObjectList.mem_list.get(options.mem_type) def setWorkCountOptions(system, options): if options.work_item_id != None: diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py index fd92a6350..d7f137896 100644 --- a/configs/dram/lat_mem_rd.py +++ b/configs/dram/lat_mem_rd.py @@ -48,6 +48,7 @@ from m5.util import addToPath from m5.stats import periodicStatDump addToPath('../') +from common import ObjectList from common import MemConfig addToPath('../../util') @@ -84,7 +85,7 @@ except: parser = optparse.OptionParser() parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_option("--mem-size", action="store", type="string", default="16MB", diff --git a/configs/dram/low_power_sweep.py b/configs/dram/low_power_sweep.py index b63921b62..7387ff45a 100644 --- a/configs/dram/low_power_sweep.py +++ b/configs/dram/low_power_sweep.py @@ -48,6 +48,7 @@ from m5.stats import periodicStatDump addToPath('../') +from common import ObjectList from common import MemConfig # This script aims at triggering low power state transitions in the DRAM @@ -61,7 +62,7 @@ parser = argparse.ArgumentParser( # Use a single-channel DDR4-2400 in 16x4 configuration by default parser.add_argument("--mem-type", default="DDR4_2400_16x4", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_argument("--mem-ranks", "-r", type=int, default=1, diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index 385708e60..f18e44e9d 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -48,6 +48,7 @@ from m5.stats import periodicStatDump addToPath('../') +from common import ObjectList from common import MemConfig # this script is helpful to sweep the efficiency of a specific memory @@ -64,7 +65,7 @@ dram_generators = { # Use a single-channel DDR3-1600 x64 (8x8 topology) by default parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_option("--mem-ranks", "-r", type="int", default=1, diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py index 35ed2afa2..4061501ba 100644 --- a/configs/example/arm/starter_fs.py +++ b/configs/example/arm/starter_fs.py @@ -56,6 +56,7 @@ import argparse m5.util.addToPath('../..') from common import SysPaths +from common import ObjectList from common import MemConfig from common.cores.arm import HPI @@ -214,7 +215,7 @@ def main(): parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=1, help = "number of memory channels") diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index b76be5f48..acd76dc87 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -55,6 +55,7 @@ import shlex m5.util.addToPath('../..') +from common import ObjectList from common import MemConfig from common.cores.arm import HPI @@ -194,7 +195,7 @@ def main(): parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", - choices=MemConfig.mem_names(), + choices=ObjectList.mem_list.get_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=2, help = "number of memory channels") diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index c9ae251d9..cad86bf79 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -49,6 +49,7 @@ from m5.util import addToPath, fatal addToPath('../') +from common import ObjectList from common import MemConfig from common import FileSystemConfig @@ -115,9 +116,10 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options): dir_ranges = [] for r in system.mem_ranges: - mem_ctrl = MemConfig.create_mem_ctrl( - MemConfig.get(options.mem_type), r, index, options.num_dirs, - int(math.log(options.num_dirs, 2)), intlv_size) + mem_type = ObjectList.mem_list.get(options.mem_type) + mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index, + options.num_dirs, int(math.log(options.num_dirs, 2)), + intlv_size) if options.access_backing_store: mem_ctrl.kvm_map=False @@ -131,7 +133,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options): mem_ctrl.port = dir_cntrl.memory # Enable low-power DRAM states if option is set - if issubclass(MemConfig.get(options.mem_type), DRAMCtrl): + if issubclass(mem_type, DRAMCtrl): mem_ctrl.enable_dram_powerdown = \ options.enable_dram_powerdown