From: Paul Berry Date: Fri, 2 Dec 2011 22:38:52 +0000 (-0800) Subject: i965: Clean up misleading defines for DWORD 2 of URB_WRITE header. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2252e5e3f1e8caece5c73df82f3ddf306baa2c91;p=mesa.git i965: Clean up misleading defines for DWORD 2 of URB_WRITE header. R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD 2 of R0 (as the name, and comments in the code, would seem to indicate). Actually they refer to bits in DWORD 2 of the header for URB_WRITE messages. This patch renames the defines to reflect what they actually mean. It also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was just hardcoded in .c files. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 75c64c0af97..614849a1917 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -254,8 +254,12 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false); brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false); - brw_clip_emit_vue(c, newvtx0, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START); - brw_clip_emit_vue(c, newvtx1, 0, 1, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END); + brw_clip_emit_vue(c, newvtx0, 1, 0, + (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START); + brw_clip_emit_vue(c, newvtx1, 0, 1, + (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END); } brw_ENDIF(p); brw_clip_kill_thread(c); diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index ffbfe944afd..12d67242ef3 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -422,14 +422,17 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) brw_MOV(p, get_addr_reg(vptr), brw_address(c->reg.inlist)); brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); - brw_clip_emit_vue(c, v0, 1, 0, ((_3DPRIM_TRIFAN << 2) | R02_PRIM_START)); + brw_clip_emit_vue(c, v0, 1, 0, + ((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START)); brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); loop = brw_DO(p, BRW_EXECUTE_1); { - brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_TRIFAN << 2)); + brw_clip_emit_vue(c, v0, 1, 0, + (_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT)); brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); @@ -439,7 +442,9 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) } brw_WHILE(p, loop); - brw_clip_emit_vue(c, v0, 0, 1, ((_3DPRIM_TRIFAN << 2) | R02_PRIM_END)); + brw_clip_emit_vue(c, v0, 0, 1, + ((_3DPRIM_TRIFAN << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); } brw_ENDIF(p); } diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c index ae84e197cbb..01f14b091be 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c @@ -321,8 +321,12 @@ static void emit_lines(struct brw_clip_compile *c, brw_imm_f(0)); brw_IF(p, BRW_EXECUTE_1); { - brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START); - brw_clip_emit_vue(c, v1, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END); + brw_clip_emit_vue(c, v0, 1, 0, + (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START); + brw_clip_emit_vue(c, v1, 1, 0, + (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END); } brw_ENDIF(p); @@ -363,7 +367,9 @@ static void emit_points(struct brw_clip_compile *c, if (do_offset) apply_one_offset(c, v0); - brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_POINTLIST << 2) | R02_PRIM_START | R02_PRIM_END); + brw_clip_emit_vue(c, v0, 1, 0, + (_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START | URB_WRITE_PRIM_END); } brw_ENDIF(p); diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index bb79bfbafdf..d94923195d5 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1413,10 +1413,10 @@ enum brw_wm_barycentric_interp_mode { #define CMD_MI_FLUSH 0x0200 -/* Various values from the R0 vertex header: - */ -#define R02_PRIM_END 0x1 -#define R02_PRIM_START 0x2 +/* Bitfields for the URB_WRITE message, DW2 of message header: */ +#define URB_WRITE_PRIM_END 0x1 +#define URB_WRITE_PRIM_START 0x2 +#define URB_WRITE_PRIM_TYPE_SHIFT 2 #include "intel_chipset.h" diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index 6d39df195f6..9b1dfbfa97b 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -188,21 +188,29 @@ void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) */ if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_START); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START)); if (key->pv_first) { brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2(c, _3DPRIM_POLYGON << 2); + brw_gs_overwrite_header_dw2( + c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); brw_gs_emit_vue(c, c->reg.vertex[1], 0); brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_END); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); brw_gs_emit_vue(c, c->reg.vertex[3], 1); } else { brw_gs_emit_vue(c, c->reg.vertex[3], 0); - brw_gs_overwrite_header_dw2(c, _3DPRIM_POLYGON << 2); + brw_gs_overwrite_header_dw2( + c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); brw_gs_emit_vue(c, c->reg.vertex[0], 0); brw_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_END); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); brw_gs_emit_vue(c, c->reg.vertex[2], 1); } } @@ -216,21 +224,29 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_START); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START)); if (key->pv_first) { brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2(c, _3DPRIM_POLYGON << 2); + brw_gs_overwrite_header_dw2( + c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); brw_gs_emit_vue(c, c->reg.vertex[1], 0); brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_END); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); brw_gs_emit_vue(c, c->reg.vertex[3], 1); } else { brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2(c, _3DPRIM_POLYGON << 2); + brw_gs_overwrite_header_dw2( + c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); brw_gs_emit_vue(c, c->reg.vertex[3], 0); brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_POLYGON << 2) | R02_PRIM_END); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); brw_gs_emit_vue(c, c->reg.vertex[1], 1); } } @@ -244,8 +260,12 @@ void brw_gs_lines( struct brw_gs_compile *c ) if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_START)); brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2(c, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END); + brw_gs_overwrite_header_dw2( + c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) + | URB_WRITE_PRIM_END)); brw_gs_emit_vue(c, c->reg.vertex[1], 1); }