From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 27 Feb 2015 13:12:13 +0000 (+0100)
Subject: report cachesize in wishbone2lasmi
X-Git-Tag: 24jan2021_ls180~2099^2~233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=225a2d4704cdf0abf7a9a1d53a1b2b2f0cb8a3bc;p=litex.git

report cachesize in wishbone2lasmi
---

diff --git a/migen/bus/wishbone2lasmi.py b/migen/bus/wishbone2lasmi.py
index 404b88ac..a2110caf 100644
--- a/migen/bus/wishbone2lasmi.py
+++ b/migen/bus/wishbone2lasmi.py
@@ -1,12 +1,14 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
+from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import split, displacer, chooser
 from migen.genlib.record import Record, layout_len
 
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
-class WB2LASMI(Module):
+class WB2LASMI(Module, AutoCSR):
 	def __init__(self, cachesize, lasmim):
+		self._cachesize = CSRStatus(8, reset=log2_int(cachesize))
 		self.wishbone = wishbone.Interface()
 
 		###