From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Jan 2022 02:46:54 +0000 (+0000)
Subject: gotten over the logic-dyslexia of what in/out mean in VHDL.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2260ca654d8552d6cb766b78df9888326b552714;p=microwatt.git

gotten over the logic-dyslexia of what in/out mean in VHDL.
BRAM can now be read/written using the contents of a file to initialise
from, at the command-line
---

diff --git a/Makefile b/Makefile
index 6bc4294..7d0d320 100644
--- a/Makefile
+++ b/Makefile
@@ -147,7 +147,7 @@ RAM_INIT_FILE=hello_world/hello_world.hex
 # Linux
 #MEMORY_SIZE=16777216 # 268435456
 #RAM_INIT_FILE=dtbImage.microwatt.hex
-SIM_MAIN_BRAM=true
+SIM_MAIN_BRAM=false
 
 FPGA_TARGET ?= ORANGE-CRAB
 
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 6cec9fe..a9fb34e 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -31,8 +31,8 @@ entity toplevel is
 	bram_we : out std_ulogic;
 	bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0)
 	);
 end entity toplevel;
diff --git a/soc.vhdl b/soc.vhdl
index 73d6292..352cfca 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -92,8 +92,8 @@ entity soc is
     bram_we : out std_ulogic;
     bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0);
 
 	-- UART0 signals:
diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index e62962f..a4a8f25 100644
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -77,6 +77,8 @@ static void mem_write(unsigned char *mem,
     }
 }
 
+#define BRAM_DEBUG
+
 int main(int argc, char **argv)
 {
 	Verilated::commandArgs(argc, argv);
@@ -143,14 +145,27 @@ int main(int argc, char **argv)
 		tick(top);
 	top->ext_rst = 1;
 
+    unsigned long long bram_do = 0;
+
 	while(!Verilated::gotFinish()) {
 		tick(top);
 
+        // read/write the memory to/from the mmap'd file (if given)
+        if (mem != NULL) {
+            top->bram_do = bram_do;
+            if (top->bram_re ) {
+                bram_do = ((unsigned long long*)mem)[top->bram_addr];
+            }
+            if (top->bram_we) {
+                mem_write(mem, top->bram_addr, top->bram_di, top->bram_sel);
+            }
+        }
+
 		uart_tx(top->uart0_txd);
 		top->uart0_rxd = uart_rx();
 
+#ifdef BRAM_DEBUG
         if (top->bram_we) {
-            mem_write(mem, top->bram_addr, top->bram_di, top->bram_sel);
             fprintf(dump, "bram wr addr %08x dout %16lx sel %x ",
                     top->bram_addr, top->bram_di, top->bram_sel);
             ascii_dump((unsigned char*)&top->bram_di, 8, dump);
@@ -160,7 +175,7 @@ int main(int argc, char **argv)
         if (next_read) {
             fprintf(dump, "bram rd addr %08x din %16lx sel %x ",
                     bram_addr, top->bram_do, top->bram_sel);
-            if (bram_data1 != top->bram_do) { // check contents
+            if ((mem != NULL) && bram_data1 != top->bram_do) { // check contents
                 fprintf(dump, "bram != %16lx ", bram_data1 );
             }
             ascii_dump((unsigned char*)&top->bram_do, 8, dump);
@@ -173,6 +188,7 @@ int main(int argc, char **argv)
         if ((mem != NULL) && next_read) {
             bram_data = ((unsigned long long*)mem)[bram_addr];
         }
+#endif // BRAM_DEBUG
 	}
 
     fclose(dump);
diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index fe26d58..4e3fb50 100644
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -26,8 +26,8 @@ entity wishbone_bram_wrapper is
     bram_we : out std_ulogic;
     bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0)
 
 	);
@@ -67,7 +67,7 @@ begin
 
     -- Verilator access to bram signals
     bram_sel <= wishbone_in.sel;
-    bram_do <= wishbone_out.dat;
+    wishbone_out.dat <= bram_do;
     bram_di <= wishbone_in.dat;
     bram_addr <= ram_addr;
     bram_we <= ram_we;