From: Gabe Black <gabeblack@google.com>
Date: Sun, 28 Apr 2019 03:37:13 +0000 (-0700)
Subject: alpha: Add some control registers to the ISA operands list.
X-Git-Tag: v19.0.0.0~916
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2268d07623910dbab50ae0f80e93068acb25cfa9;p=gem5.git

alpha: Add some control registers to the ISA operands list.

These will be used in the in-ISA HWREI implementation.

Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 646286605..f77b1f9c9 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -76,6 +76,7 @@ output exec {{
 #include <cmath>
 
 #include "arch/alpha/decoder.hh"
+#include "arch/alpha/kernel_stats.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
 #include "arch/generic/memhelpers.hh"
@@ -198,6 +199,8 @@ def operands {{
     'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
     'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
     'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
+    'LockFlag': ('ControlReg', 'uq', 'MISCREG_LOCKFLAG', None, 1),
+    'IprExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),