From: SergeyDegtyar Date: Wed, 28 Aug 2019 06:47:03 +0000 (+0300) Subject: Add tests for ecp5 X-Git-Tag: working-ls180~1084^2~14 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2270ead09fb4695442c66fe5c06445235f390f2b;p=yosys.git Add tests for ecp5 --- diff --git a/Makefile b/Makefile index 9cfa6a0de..d94ab2465 100644 --- a/Makefile +++ b/Makefile @@ -700,6 +700,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..5829fef5f --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFN +select -assert-count 2 t:DFFSR +select -assert-count 7 t:LUT4 +select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ecp5/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..07470c5ba --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFE +select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..169c5978e --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 45 t:L6MUX21 +select -assert-count 183 t:LUT4 +select -assert-count 79 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..2c77304a1 --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,7 @@ +read_verilog latches.v +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v new file mode 100644 index 000000000..b0585264b --- /dev/null +++ b/tests/ecp5/latches_tb.v @@ -0,0 +1,57 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..9fdeb0d16 --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,22 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v new file mode 100644 index 000000000..be69374eb --- /dev/null +++ b/tests/ecp5/memory_tb.v @@ -0,0 +1,79 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..47a965dd3 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 30 t:LUT4 +select -assert-count 7 t:L6MUX21 +select -assert-count 12 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..22c495784 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,33 @@ +set -e +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for t in *_tb.v; do + echo "all:: run-$t" + echo "run-$t: ${t%_tb.v}_synth.v" + echo " @echo 'Running $t..'" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ecp5/cells_sim.v" + echo " @vvp -N ${t%_tb.v}_testbench" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D