From: Chad Versace <chad.versace@linux.intel.com>
Date: Thu, 18 Jul 2013 17:04:17 +0000 (-0700)
Subject: i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2273b652bb884a6188af7f8d063d0d0fc5497054;p=mesa.git

i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS

Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.

In blorp, change only the PS packet, because the VS packet is disabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 0c08584baea..0fa352aebfe 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -616,6 +616,8 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
                             const brw_blorp_params *params,
                             uint32_t wm_push_const_offset)
 {
+   uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+
    /* Make sure the push constants fill an exact integer number of
     * registers.
     */
@@ -630,7 +632,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
              (7 - 2));
    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
    OUT_BATCH(0);
-   OUT_BATCH(wm_push_const_offset);
+   OUT_BATCH(wm_push_const_offset | mocs);
    OUT_BATCH(0);
    OUT_BATCH(0);
    OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 7369a9c7cfc..0340da4ba12 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -63,6 +63,8 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
+      uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+
       BEGIN_BATCH(7);
       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
       OUT_BATCH(brw->vs.push_const_size);
@@ -70,7 +72,7 @@ upload_vs_state(struct brw_context *brw)
       /* Pointer to the VS constant buffer.  Covered by the set of
        * state flags from gen6_prepare_wm_contants
        */
-      OUT_BATCH(brw->vs.push_const_offset);
+      OUT_BATCH(brw->vs.push_const_offset | mocs);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 8f9037136a6..1bc6e2ec231 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -141,6 +141,8 @@ upload_ps_state(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
+      uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
+
       BEGIN_BATCH(7);
       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 
@@ -150,7 +152,7 @@ upload_ps_state(struct brw_context *brw)
       /* Pointer to the WM constant buffer.  Covered by the set of
        * state flags from gen6_upload_wm_push_constants.
        */
-      OUT_BATCH(brw->wm.push_const_offset);
+      OUT_BATCH(brw->wm.push_const_offset | mocs);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);