From: lkcl <lkcl@web>
Date: Sat, 13 Feb 2021 11:51:08 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~193
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=227571dff826969bceb21ac0cc3414b1ad3b6815;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index eb9d90095..a0dc561ae 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -6,6 +6,8 @@
 
 this extension amalgamates bitnanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.  Vectorisation and SIMD are removed: these are straight scalar (element) ooerations.  Vectorisation Context is provided by [[openpower/sv]].
 
+ternaryv is experimental and is the only operation that may be considered a "Packed SIMD".  It is added as a variant of the already well-justified ternary operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs.  Other vendors of ISAs are buying FPGA companies to achieve a similar objective.
+
 # summary
 
 minor opcode allocation