From: whitequark <cz@m-labs.hk>
Date: Mon, 3 Jun 2019 07:54:28 +0000 (+0000)
Subject: vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22792c3aca959259bfe0ba3c569b0d138ef796a8;p=nmigen.git

vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
---

diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py
index 778e9c7..b8852d1 100644
--- a/nmigen/vendor/fpga/lattice_ice40.py
+++ b/nmigen/vendor/fpga/lattice_ice40.py
@@ -119,6 +119,12 @@ class LatticeICE40Platform(TemplatedPlatform):
     def _get_io_buffer(self, pin, port, extras):
         m = Module()
 
+        if "GLOBAL" in extras:
+            is_global_input = bool(extras["GLOBAL"])
+            del extras["GLOBAL"]
+        else:
+            is_global_input = False
+
         if "i" in pin.dir and pin.xdr == 2:
             i0_ff = Signal.like(pin.i0, name="{}_ff".format(pin.i0.name))
             i1_ff = Signal.like(pin.i1, name="{}_ff".format(pin.i1.name))
@@ -162,9 +168,11 @@ class LatticeICE40Platform(TemplatedPlatform):
                 io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
 
             if "i" in pin.dir:
-                if pin.xdr < 2:
+                if pin.xdr == 0 and is_global_input:
+                    io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
+                elif pin.xdr < 2:
                     io_args.append(("o", "D_IN_0",  pin.i[bit]))
-                if pin.xdr == 2:
+                elif pin.xdr == 2:
                     # Re-register both inputs before they enter fabric. This increases hold time
                     # to an entire cycle, and adds one cycle of latency.
                     io_args.append(("o", "D_IN_0",  i0_ff))
@@ -172,7 +180,7 @@ class LatticeICE40Platform(TemplatedPlatform):
             if "o" in pin.dir:
                 if pin.xdr < 2:
                     io_args.append(("i", "D_OUT_0", pin.o[bit]))
-                if pin.xdr == 2:
+                elif pin.xdr == 2:
                     # Re-register negedge output after it leaves fabric. This increases setup time
                     # to an entire cycle, and doesn't add latency.
                     io_args.append(("i", "D_OUT_0", pin.o0[bit]))
@@ -181,7 +189,10 @@ class LatticeICE40Platform(TemplatedPlatform):
             if pin.dir in ("oe", "io"):
                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 
-            m.submodules += Instance("SB_IO", *io_args)
+            if is_global_input:
+                m.submodules += Instance("SB_GB_IO", *io_args)
+            else:
+                m.submodules += Instance("SB_IO", *io_args)
 
         return m
 
diff --git a/nmigen/vendor/ice40_hx1k_blink_evn.py b/nmigen/vendor/ice40_hx1k_blink_evn.py
index 1f44882..cc6d5a5 100644
--- a/nmigen/vendor/ice40_hx1k_blink_evn.py
+++ b/nmigen/vendor/ice40_hx1k_blink_evn.py
@@ -12,7 +12,8 @@ class ICE40HX1KBlinkEVNPlatform(IceBurnProgrammerMixin, LatticeICE40Platform):
         ("clk3p3", 3.3e6),
     ]
     resources = [
-        Resource("clk3p3", 0, Pins("13", dir="i"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
+        Resource("clk3p3", 0, Pins("13", dir="i"),
+                 extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
 
         Resource("user_led", 0, Pins("59", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
         Resource("user_led", 1, Pins("56", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
diff --git a/nmigen/vendor/icestick.py b/nmigen/vendor/icestick.py
index 4d1ecfd..f2f2da6 100644
--- a/nmigen/vendor/icestick.py
+++ b/nmigen/vendor/icestick.py
@@ -12,7 +12,8 @@ class ICEStickPlatform(IceStormProgrammerMixin, LatticeICE40Platform):
         ("clk12", 12e6),
     ]
     resources = [
-        Resource("clk12", 0, Pins("21", dir="i"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
+        Resource("clk12", 0, Pins("21", dir="i"),
+                 extras={"GLOBAL": "1", "IO_STANDARD": "SB_LVCMOS33"}),
 
         Resource("user_led", 0, Pins("99", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
         Resource("user_led", 1, Pins("98", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
diff --git a/nmigen/vendor/tinyfpga_bx.py b/nmigen/vendor/tinyfpga_bx.py
index 50ced5d..24f7c33 100644
--- a/nmigen/vendor/tinyfpga_bx.py
+++ b/nmigen/vendor/tinyfpga_bx.py
@@ -12,7 +12,8 @@ class TinyFPGABXPlatform(TinyProgrammerMixin, LatticeICE40Platform):
         ("clk16", 16e6),
     ]
     resources = [
-        Resource("clk16", 0, Pins("B2", dir="i"), extras={"IO_STANDARD": "SB_LVCMOS33"}),
+        Resource("clk16", 0, Pins("B2", dir="i"),
+                 extras={"GLOBAL": 1, "IO_STANDARD": "SB_LVCMOS33"}),
 
         Resource("user_led", 0, Pins("B3", dir="o"), extras={"IO_STANDARD": "SB_LVCMOS33"}),