From: whitequark Date: Wed, 3 Apr 2019 14:59:01 +0000 (+0000) Subject: hdl.ast: handle a common typo, such as Signal(1, True). X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22887725ef15b0c910d3a0d26f61503620a24e54;p=nmigen.git hdl.ast: handle a common typo, such as Signal(1, True). --- diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index 75dad9b..b64f7bf 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -581,6 +581,8 @@ class Signal(Value, DUID): attrs=None, decoder=None, src_loc_at=0): super().__init__(src_loc_at=src_loc_at) + if name is not None and not isinstance(name, str): + raise TypeError("Name must be a string, not '{!r}'".format(name)) self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal") if shape is None: diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py index 9f20d17..608870f 100644 --- a/nmigen/test/test_hdl_ast.py +++ b/nmigen/test/test_hdl_ast.py @@ -429,6 +429,12 @@ class SignalTestCase(FHDLTestCase): s2 = Signal(name="sig") self.assertEqual(s2.name, "sig") + def test_name_bad(self): + with self.assertRaises(TypeError, + msg="Name must be a string, not 'True'"): + # A common typo: forgetting to put parens around width and signedness + Signal(1, True) + def test_reset(self): s1 = Signal(4, reset=0b111, reset_less=True) self.assertEqual(s1.reset, 0b111)